MPF5024AMBA0ES datasheet(42/93 Pages) NXP

42 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

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Product data sheet

Rev. 1 — 15 April 2020

42 / 93

• When ENx is in low state, ENx_S flag is set to 0.

• When ENx is in high state, ENx_S flag is set to 1.

14.9.9 TBBEN

The TBBEN is an input pin provided to allow the user to program the mirror registers

in order to operate the device with a custom configuration as well as programming the

default values on the OTP fuses.

• When TBBEN pin is pulled low to ground, the device is operating in normal mode.

• When TBBEN pin is pulled high to V1P5D, the device enables the TBB configuration

mode.

See Section 17 "OTP/TBB and hardwire default configurations" for details on TBB and

OTP operation.

When TBBEN pin is pulled high to V1P5D the following conditions apply:

• The device uses a fixed I2C device address (0x08)

• Disable the watchdog operation, including WDI monitoring and internal watchdog timer

• Disable the CRC and I2C secure write mechanism while no power up event is present

(TBB/OTP programming mode).

Disabling the watchdog operation may be required for in-line MCU programming where

output voltages are required but watchdog operation should be completely disabled.

14.9.10 XFAILB

XFAILB is a bidirectional pin with an open drain output used to synchronize the power

up and power down sequences of two or more PMICs. It should normally be pulled up

externally to V1P5A supply.

The OTP_XFAILB_EN bit is used to enable or disable the XFAILB mode of operation.

• When OTP_XFAILB_EN = 0, the XFAILB mode is disabled and any events on this pin

are ignored.

• When OTP_XFAILB_EN = 1, the XFAILB mode is enabled

When the XFAILB mode is enabled, and the PF5024 has a turn off event generated by

an internal fault, the XFAILB pin is asserted low 20 µs before starting the power down

sequence.

A power down event caused by the following conditions will assert the XFAILB pin:

• Fault timer expired

• FAULT_CNT = FAULT_MAX_CNT (Regulator fault counter max out)

• WD_EVENT_CNT = WD_MAX_CNT (Watchdog event counter max out)

• Power up failure

• Thermal shutdown

• Hard WD event

The XFAILB pin is forced low during the Off mode.

During the system On state, if the XFAILB pin is externally pulled low, it will detect an

XFAIL event after a 20 µs debounce. When an XFAIL event is detected, the XFAILB pin

is asserted low internally and the device starts a power down sequence.

MPF5024AMBA0ES Datasheet(PDF) 42 Page - NXP Semiconductors

MPF5024AMBA0ES Datasheet(HTML) 42 Page - NXP Semiconductors

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