MPF5024AMBA0ES datasheet(82/93 Pages) NXP

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NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

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Product data sheet

Rev. 1 — 15 April 2020

82 / 93

18.3 ABIST verification

The PF5024 ASIL B implements an ABIST verification of all output voltage monitors as

well as PGOOD pin. The ABIST verification on the output voltage monitoring behaves as

follows:

• Device tests the OV comparators for each individual SWx supply during the self-test

routine

• Device tests the UV comparators for each individual SWx supply during the self-test

routine

• During the ABIST verification, it is required to ensure the corresponding OV/UV

comparators are able to toggle, which in turn is a sign of the integrity of these functions

• If any of the comparators is not able to toggle, a warning bit is set on the I2C register

map.

– The ABIST_OV1 register contains the AB_SWx_OV bits for all external regulators.

– The ABIST_UV1 register contains the AB_SWx_UV bits for all external regulators.

• The ABIST registers are cleared or overwritten each time the ABIST check is

performed.

• The ABIST registers are part of the secure registers and will require an I2C secure write

to be cleared if this feature is enabled.

Once ABIST check is performed, the PF5024 can proceed with the power up sequence

and the MCU should be able to request the value of these registers and learn if ABIST

failed for any of the voltage monitors.

The AB_RUN bit is provided to perform an ABIST verification on demand.

When the AB_RUN bit is set to 1, the control logic perform an ABIST verification on all

OV/UV monitoring circuits. When the ABIST verification is finished, the AB_RUN bit self-

clear to 0 and a new ABIST verification can be commanded as needed.

When the secure write feature is enabled, the system must perform a secure write

sequence in order to start an ABIST verification on demand.

When the PF5024 performs an ABIST verification on demand, the OV/UV fault

monitoring is blanked for a maximum period of 200 µs. During this time, the system must

ensure it is in a safe state, or it is safe to perform this action without violating the safety

goals of the system.

If a failure on the OV/UV monitor is detected during the ABIST on demand request,

the PMIC will assert the corresponding ABIST flags. It is responsibility of the system to

perform a diagnostic check after each ABIST verification to ensure it places the system in

safe state if an ABIST fault is detected.

19 IC level quiescent current requirements

Table 59. Quiescent current requirements

All parameters are specified at TA = −40 to 125 °C, unless otherwise noted. Typical values are characterized at VIN = 5.0 V

and TA = 25 °C, unless otherwise noted.

Symbol

Parameter

Min

Typ

Max

Unit

ILPOFF

LP_Off state

LPM_OFF = 0

VIN > UVDET

—

150

µA

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