MPF5024AMBA0ES datasheet(19/93 Pages) NXP

19 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

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Product data sheet

Rev. 1 — 15 April 2020

19 / 93

aaa-030045

Self

Test

RESETBMCU

STEST done

(internal signal)

Regulator Outputs

(enable signals)

PWRON

V1P5D

UVDET

VIN

Fuse

Load

1.6 V

tstest_done

treg2reset

tvin_rise

tfirst

Figure 6. Startup with PWRON pulled up

Table 15. Startup timing requirements (PWRON pulled up)

Symbol

Parameter

Min

Typ

Max

Unit

tvin_rise

Rise time of VIN from VPWR application to UVDET

(system dependent)

—

1500

µs

tstest_done

Time from VIN crossing UVDET to fist slot of power up

sequence

—

1.5

14.4 IC startup timing with PWRON pulled low during VIN application

It is possible that PWRON is held low when VIN is applied. By default, LPM_OFF bit

is reset to 0 upon crossing UVDET, therefore the PF5024 remains in the LP_Off state

as described in Section 13.1.2 "LP_Off state". In this scenario, the quiescent current in

the LP_Off state is kept to a minimum. When PWRON goes high with LPM_OFF = 0,

the PMIC startup is expected to take longer, since it has to enable most of the internal

circuits and perform the self-test before starting a power up sequence.

Figure 7 shows startup timing with LPM_OFF = 0.

MPF5024AMBA0ES Datasheet(PDF) 19 Page - NXP Semiconductors

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