MPF5024AMBA0ES datasheet(35/93 Pages) NXP

35 / 93 page

NXP Semiconductors

PF5024

Power management integrated circuit (PMIC) for high performance applications

PF5024

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Product data sheet

Rev. 1 — 15 April 2020

35 / 93

• When the mask bit is 0, the INTB pin is pulled low as long as the corresponding latch

bit is set.

• The sense bit XXXX_S: if available, the sense bit provides the actual status of the

signal triggering the interrupt.

The INTB pin is a reflection of an “OR” logic of all the interrupt status bits which control

the pin.

Interrupts are stored in two levels on the interrupts registers. At first level, the SYS_INT

event.

The corresponding SYS_INT bits is set as long as the INTB pin is programmed to assert

with any of the interrupt bits of the respective interrupt registers.

• STATUS1_I: this bit is set when the interrupt is generated within the INT STATUS1

• STATUS2_I: this bit is set when the interrupt is generated within the INT STATUS2

• MODE_I: this bit is set when the interrupt is generated within the SW MODE INT

• ILIM_I: this bit is set when the interrupt is generated within any of the SW ILIM INT

• UV_I: this bit is set when the interrupt is generated within any of the SW UV INT

• OV_I: this bit is set when the interrupt is generated within any of the SW OV register

• PWRON_I: this bit is set when the interrupt is generated within the PWRON INT

• EWARN_I: is set when an early warning event occurs to indicate an imminent

shutdown

The SYS_INT bits are set when the INTB pin is asserted by any of the second level

interrupt bits that have not been masked in their corresponding mask registers. When

the second level interrupt bit is cleared, the corresponding first level interrupt bit on the

SYS_INT register will be cleared automatically.

The INTB pin will remain asserted if any of the first level interrupts bit is set, and it will be

de-asserted only when all the unmasked second level interrupts are cleared and thus all

the first level interrupts are cleared as well.

At second level the remaining registers provide the exact source for the interrupt event.

Table 26 shows a summary of the interrupt latch, mask and sense pins available on the

PF5024.

Table 26. Interrupt registers

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

INT STATUS1

SDWN_I

FREQ_RDY_I

CRC_I

PWRUP_I

PWRDN_I

—

PGOOD_I

VIN_OVLO_I

INT MASK1

SDWN_M

FREQ_RDY_M

CRC_M

PWRUP_M

PWRDN_M

—

PGOOD_M

VIN_OVLO_M

INT SENSE1

—

PGOOD_S

VIN_OVLO_S

THERM INT

WDI_I

FSYNC_FLT_I

THERM_155_I

THERM_140_I

THERM_125_I

THERM_110_I

THERM_95_I

THERM_80_I

THERM MASK

WDI_M

FSYNC_FLT_M

THERM_155_M

THERM_140_M

THERM_125_M

THERM_110_M

THERM_95_M

THERM_80_M

THERM SENSE

WDI_S

FSYNC_FLT_S

THERM_155_S

THERM_140_S

THERM_125_S

THERM_110_S

THERM_95_S

THERM_80_S

SW MODE INT

—

SW4_MODE_I

SW3_MODE_I

SW2_MODE_I

SW1_MODE_I

SW MODE MASK

—

SW4_MODE_M

SW3_MODE_M

SW2_MODE_M

SW1_MODE_M

SW ILIM INT

—

SW4_ILIM_I

SW3_ILIM_I

SW2_ILIM_I

SW1_ILIM_I

SW ILIM MASK

—

SW4_ILIM_M

SW3_ILIM_M

SW2_ILIM_M

SW1_ILIM_M

SW ILIM SENSE

—

SW4_ILIM_S

SW3_ILIM_S

SW2_ILIM_S

SW1_ILIM_S

SW UV INT

—

SW4_UV_I

SW3_UV_I

SW2_UV_I

SW1_UV_I

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