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MPF5024AMBA0ES Datasheet(PDF) 17 Page - NXP Semiconductors

Part # MPF5024AMBA0ES
Description  Power management integrated circuit (PMIC) for high performance applications
PDF  93 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPF5024AMBA0ES Datasheet(HTML) 17 Page - NXP Semiconductors

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NXP Semiconductors
PF5024
Power management integrated circuit (PMIC) for high performance applications
PF5024
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2020. All rights reserved.
Product data sheet
Rev. 1 — 15 April 2020
17 / 93
Table 11. Fail-safe OK timer configuration
OTP_FS_OK_TIME[2:0]
FS_CNT decrease period (min)
000
1
001
5
010
10
011
15
100
20
101
30
110
45
111
60
When the fail-safe OK timer reaches the configured time during the system On state, the
state machine decreases the FS_CNT[3:0] bits by one and starts a new count until the
FS_CNT[3:0] is 0x00. The FS_CNT[3:0] may be manually cleared during the system on
state if the system wants to control this counter manually.
14 General device operation
14.1 UVDET
UVDET works as the main operation threshold for the PF5024. Crossing UVDET on the
rising edge is a mandatory condition for OTP fuses to be loaded into the mirror registers
and allows the main PF5024 operation.
If VIN is below the UVDET threshold, the device remains in an unpowered state. A
200 mV hysteresis is implemented on the UVDET comparator to set the falling threshold.
Table 12. UVDET threshold
Symbol
Parameter
Min
Typ
Max
Unit
UVDET
Rising UVDET
2.7
2.8
2.9
V
UVDET
Falling UVDET
2.5
2.6
2.7
V
14.2 VIN OVLO condition
The VIN_OVLO circuit monitors the main input supply of the PF5024. When this block is
enabled, the PF5024 monitors its input voltage and can be programmed to react to an
overvoltage in two ways:
• When the VIN_OVLO_SDWN = 0, the VIN_OVLO event triggers an OVLO interrupt but
does not turn off the device
• When the VIN_OVLO_SDWN = 1, the VIN_OVLO event initiates a power down
sequence
When the VIN_OVLO_EN = 0, the OVLO monitor is disabled and when the
VIN_OVLO_EN = 1, the OVLO monitor is enabled. The default configuration of the
VIN_OVLO_EN bit is set by the OTP_VIN_OVLO_EN bit in OTP. Likewise, the default
value of the VIN_OVLO_SDWN bit is set by the OTP_VIN_OVLO_SDWN upon power
up.
During a power up transition, if the OTP_VIN_OVLO_SDWN = 0 the device allows the
external regulators to come up and the PF5024 announces the VIN_OVLO condition



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