MM912F634CV2AP datasheet(22/335 Pages) FREESCALE

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Electrical Characteristics

Dynamic Electrical Characteristics

MM912F634

Freescale Semiconductor

Table 31. Dynamic Electrical Characteristics - Window Watchdog

Ratings

Symbol

Min

Typ

Max

Unit

Initial Non-window Watchdog Timeout

tIWDTO

110

150

190

Watchdog Timeout Accuracy - not trimmed

WDAC

-35

Watchdog Timeout Accuracy - trimmed

WDACT

-5.0

5.0

Table 32. Dynamic Electrical Characteristics - High Side Drivers - HS

Ratings

Symbol

Min

Typ

Max

Unit

High Side Operating Frequency(25)

Load Condition: CLOAD ≤ 2.2 nF; RLOAD ≥ 500 Ω

fHS

kHz

Note:

25. Guaranteed by design.

Table 33. Dynamic Electrical Characteristics - Low Side Drivers - LS

Ratings

Symbol

Min

Typ

Max

Unit

Low Side Operating Frequency

fLS

kHz

Table 34. Dynamic Electrical Characteristics - LIN Physical Layer Interface - LIN

Ratings

Symbol

Min

Typ

Max

Unit

Bus Wake-up Deglitcher (Sleep and Stop Mode)

tPROPWL

100

µs

Fast Bit Rate (Programming Mode)

BRFAST

100

kBit/s

Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF)(26)

tREC_PD

6.0

µs

Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR

tREC_SYM

-2.0

2.0

µs

LIN Driver - 20.0 kBit/s; Bus load conditions (CBUS; RBUS): 1.0 nF; 1.0 kΩ / 6,8 nF;660 Ω / 10 nF;500 Ω. Measurement thresholds: 50% of TXD

signal to LIN signal threshold defined at each parameter. See Figure 5 and Figure 6.

Duty Cycle 1:

THREC(MAX) = 0.744 x VSUP

THDOM(MAX) = 0.581 x VSUP

7.0 V

≤ VSUP ≤ 18 V; tBit = 50 µs;

D1 = tBUS_REC(MIN)/(2 x tBit)

0.396

Duty Cycle 2:

THREC(MIN) = 0.422 x VSUP

THDOM(MIN) = 0.284 x VSUP

7.6 V

≤ VSUP ≤ 18 V; tBIT = 50 µs

D2 = tBUS_REC(MAX)/(2 x tBIT)

0.581

LIN Driver - 10.0 kBit/s; Bus load conditions (CBUS; RBUS): 1.0 nF; 1.0 kΩ / 6,8 nF;660 Ω / 10 nF;500 Ω. Measurement thresholds: 50% of TXD

signal to LIN signal threshold defined at each parameter. See Figure 5 and Figure 7.

Duty Cycle 3:

THREC(MAX) = 0.778 x VSUP

THDOM(MAX) = 0.616 x VSUP

7.0 V

≤ VSUP ≤ 18 V; tBIT = 96 µs

D3 = TBUS_REC(MIN)/(2 x tBIT)

0.417

Duty Cycle 4:

THREC(MIN) = 0.389 x VSUP

THDOM(MIN) = 0.251 x VSUP

7.6 V

≤ VSUP ≤ 18 V; tBIT = 96 µs

D4 = tBUS_REC(MAX)/(2 x tBIT)

0.590

MM912F634CV2AP Datasheet(PDF) 22 Page - Freescale Semiconductor, Inc

MM912F634CV2AP Datasheet(HTML) 22 Page - Freescale Semiconductor, Inc

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