MM912F634CV2AP datasheet(77/335 Pages) FREESCALE

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Functional Description and Application Information

Window Watchdog

MM912F634

Freescale Semiconductor

4.9

Window Watchdog

The MM912F634 analog die includes a configurable window watchdog, which is active in Normal mode. The watchdog module

is based on a separate clock source (fBASE) operating independent from the MCU based D2DCLK clock. The watchdog timeout

(tWDTO) can be configured between 10 ms and 1280 ms (typ.) using the Watchdog Register (WDR).

During Low Power mode, the watchdog feature is not active, a D2D read during Stop mode will have the WDOFF bit set.

To clear the watchdog counter, a alternating write must be performed to the Watchdog Service Register (WDSR). The first write

after the RESET_A has been released has to be 0xAA. The next one must be 0x55.

After the RESET_A has been released, there will be a standard (non-window) watchdog active with a fixed timeout of tIWDTO.

The Watchdog Window Open (WDWO) bit is set during that time and the window watchdog can be configured (WDR) without

changing the initial timeout, and can be trimmed using the trim value given in the MCU trimming Flash section. See Section 4.25,

“MM912F634 - Analog Die Trimming".

Figure 21. MM912F634 Analog Die Watchdog Operation

To enable the window watchdog, the initial counter reset has to be performed by writing 0xAA to the Watchdog Service Register

(WDSR) before tIWDTO is reached.

If the tIWDTO timeout is reached with no counter reset or a value different from 0xAA was written to the WDSR, a watchdog reset

will occur.

Once entering Window Watchdog mode, the first half of the time tWDTO forbids a counter reset. To reset the watchdog counter,

an alternating write of 0x55 and 0xAA must be performed within the second half of the tWDTO. A Window Open (WDWO) flag will

indicate the current status of the window. A timeout or wrong value written to the WDSR will force a watchdog reset.

For debug purpose, the watchdog can be completely disabled by applying VTST to the TCLK pin while TEST_A is grounded. The

watchdog will be disabled as long as VTST is present. The watchdog is guaranteed functional for VTSTEN. The WDOFF bit will

indicate the watchdog being disabled. The WDSR register will reset to default once the watchdog is disabled. Once the watchdog

is re-enabled, the initial watchdog sequence has to be performed.

During Low Power mode, the Watchdog clock is halted and the Watchdog Service Register (WDSR) is reset to the default state.

Window Watch Dog

Window Closed

Window Watch Dog

Window Open

Standard Initial Watch Dog (no window)

tIWDTO

WD Register

WRITE = 0x55

Initial WD Reg.

WRITE = 0xAA

Window Watch Dog

Window Closed

Window Watch Dog

Window Open

tWDTO / 2

Window WD timing (tWDTO)

WD Register

WRITE = 0xAA

(to be continued)

MM912F634CV2AP Datasheet(PDF) 77 Page - Freescale Semiconductor, Inc

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