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MM912F634CV2AP Datasheet(PDF) 67 Page - Freescale Semiconductor, Inc

Part # MM912F634CV2AP
Description  Integrated S12 Based Relay Driver with LIN
PDF  335 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MM912F634CV2AP Datasheet(HTML) 67 Page - Freescale Semiconductor, Inc

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Functional Description and Application Information
Interrupts
MM912F634
Freescale Semiconductor
67
4.6.1.2
Interrupt Vector Emulation by Priority
To allow a vector based interrupt handling by the MCU, the number of the highest prioritized interrupt pending is returned in the
Interrupt Vector Register. To allow an offset based vector table, the result is pre-shifted (multiple of 2). Reading this register will
not acknowledge an interrupt. An additional D2D access is necessary to serve the specific module.
4.6.1.2.1
Interrupt Vector Register (IVR)
The following table is listing all MM912F634 analog die interrupt sources with the corresponding priority.
Table 79. ISR - Register Field Descriptions
Field
Description
0 - VSI
VSI - Voltage Status Interrupt combining the following sources:
• Low Battery Interrupt
• Low Voltage Interrupt
• High Voltage Interrupt
• Voltage Regulator Over-voltage Interrupt
• Voltage Regulator High Temperature Interrupt
1 - CH0
CH0 - TIM Channel 0 Interrupt
2 - CH1
CH1 - TIM Channel 1 Interrupt
3 - CH2
CH2 - TIM Channel 2 Interrupt
4 - CH3
CH3 - TIM Channel 3 Interrupt
5 - TOV
TOV - Timer Overflow Interrupt
6 - ERR
ERR - SCI Error Interrupt
7 - TX
TX - SCI Transmit Interrupt
8 - RX
RX - SCI Receive Interrupt
9 - SCI
SCI - ADC Sequence Complete Interrupt
10 - LINOT
LINOT - LIN Driver Over-temperature Interrupt
11 - HSOT
HSOT - High Side Over-temperature Interrupt
12 - LSOT
LSOT - Low Side Over-temperature Interrupt
13 - HOT
HOT - HSUP Over-temperature Interrupt
Table 80. Interrupt Vector Register (IVR)
Offset(64) 0x02
Access: User read
76
543
210
R
0
0
IRQ
W
Note:
64. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 81. IVR - Register Field Descriptions
Field
Description
5:0
IRQ
Represents the highest prioritized interrupt pending. See Table 82 In case no interrupt is pending, the result will be 0.



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