MM912F634CV2AP datasheet(95/335 Pages) FREESCALE

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Functional Description and Application Information

PWM Control Module (PWM8B2C)

MM912F634

Freescale Semiconductor

4.13.3.7

PWM Channel Duty Registers (PWMDTYx)

NOTE

Reads of this register return the most recent value written. Reads do not necessarily return

the value of the currently active duty due to the double buffering scheme.

There is a dedicated duty register for each channel. The value in this register determines the duty of the associated PWM

channel. The duty value is compared to the counter and if it is equal to the counter value a match occurs and the output changes

state.

The duty registers for each channel are double buffered, so if they change while the channel is enabled, the change will NOT

take effect until one of the following occurs:

•

The effective period ends

•

The counter is written (counter resets to $00)

•

The channel is disabled

In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform, not some variation in

between. If the channel is not enabled, then writes to the duty register will go directly to the latches as well as the buffer.

See Section 4.13.4.2.3, “PWM Period and Duty"” for more information.

NOTE

Depending on the polarity bit, the duty registers will contain the count of either the high time

or the low time. If the polarity bit is one, the output starts high and then goes low when the

duty count is reached, so the duty registers contain a count of the high time. If the polarity

bit is zero, the output starts low and then goes high when the duty count is reached, so the

duty registers contain a count of the low time.

To calculate the output duty cycle (high time as a% of period) for a particular channel:

•

Polarity = 0 (PPOL x =0)

– Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%

•

Polarity = 1 (PPOLx = 1)

– Duty Cycle = [PWMDTYx / PWMPERx] * 100%

For boundary case programming values, please refer to Section 4.13.4.2.7, “PWM Boundary Cases"”.

Figure 24. PWM Channel Duty Registers (PWMDTYx)

Offset(86) 0x68/0x69

Access: User read/write

543

210

Bit 7

Bit 0

Reset

000

Note:

86. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

MM912F634CV2AP Datasheet(PDF) 95 Page - Freescale Semiconductor, Inc

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