MM912F634CV2AP datasheet(98/335 Pages) FREESCALE

98 / 335 page

Functional Description and Application Information

PWM Control Module (PWM8B2C)

MM912F634

Freescale Semiconductor

NOTE

Clock SA = Clock A / (2 * PWMSCLA)

When PWMSCLA = $00, PWMSCLA value is considered a full scale value of 256. Clock A

is thus divided by 512.

Clock A is used as an input to an 8-bit down counter. This down counter loads a user programmable scale value from the scale

register (PWMSCLA). When the down counter reaches one, a pulse is output and the 8-bit counter is re-loaded. The output signal

from this circuit is further divided by two. This gives a greater range with only a slight reduction in granularity. Clock SA equals

clock A divided by two times the value in the PWMSCLA register.

NOTE

Clock SB = Clock B / (2 * PWMSCLB)

When PWMSCLB = $00, PWMSCLB value is considered a full scale value of 256. Clock B

is thus divided by 512.

Similarly, clock B is used as an input to an 8-bit down counter followed by a divide by two producing clock SB. Thus, clock SB

equals clock B divided by two times the value in the PWMSCLB register.

As an example, consider the case in which the user writes $FF into the PWMSCLA register. Clock A for this case will be E divided

by 4. A pulse will occur at a rate of once every 255x4 E cycles. Passing this through the divide by two circuit produces a clock

signal at an E divided by 2040 rate. Similarly, a value of $01 in the PWMSCLA register when clock A is E divided by 4 will produce

a clock at an E divided by 8 rate.

NOTE

Writing to the scale registers while channels are operating can cause irregularities in the

PWM outputs.

Writing to PWMSCLA or PWMSCLB causes the associated 8-bit down counter to be re-loaded. Otherwise, when changing rates

the counter would have to count down to $01 before counting at the proper rate. Forcing the associated counter to re-load the

scale register value every time PWMSCLA or PWMSCLB is written prevents this.

4.13.4.1.3

Clock Select

NOTE

Changing clock control bits while channels are operating can cause irregularities in the PWM

outputs.

Each PWM channel has the capability of selecting one of two clocks. For channels 0 the clock choice is clock A or clock SA. For

channels 1 the choice is clock B or clock SB. The clock selection is done with the PCLKx control bits in the PWMCTL register.

4.13.4.2

PWM Channel Timers

The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period register, and a duty

register (each are 8-bit). The waveform output period is controlled by a match between the period register and the value in the

counter. The duty is controlled by a match between the duty register and the counter value, and causes the state of the output to

change during the period. The starting polarity of the output is also selectable on a per channel basis. Shown in Figure 26 is the

block diagram for the PWM timer.

MM912F634CV2AP Datasheet(PDF) 98 Page - Freescale Semiconductor, Inc

MM912F634CV2AP Datasheet(HTML) 98 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL