MM912F634CV2AP datasheet(29/335 Pages) FREESCALE

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Electrical Characteristics

Dynamic Electrical Characteristics

MM912F634

Freescale Semiconductor

3.6.2.3

Reset, Oscillator and Internal Clock Generation

3.6.2.3.1

Startup & FLL Characteristics

Table 39 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be

found in the Clock and Reset Generator (CRG) block description.

Table 39. Startup & FLL Characteristics

Rating

Symbol

Min

Typ

Max

Unit

Internal Reference Frequency(40) (-40

°C ≤ TJ ≤ 105 °C)

fIREF_TRIM

31.36

32.64

kHz

Internal Reference Frequency(40) (-40

°C ≤ TJ ≤ 140 °C)

fIREF_TRIM

30.40

33.60

kHz

Allowed frequency range for FLL Reference Clock

fFLLREF

25.52

kHz

DCO Frequency locking range

fDCO

MHz

DCO minimum frequency

fDCO_MIN

MHz

DCO stabilization delay in frequency locked loop

tSTAB

-0.3

Lock Detection

ΔLOCK |

1.5

%(41)

Un-lock Detection

ΔUNLOCCK |

0.5

2.5

%(41)

DCO quantization error

ΔtDCO(42)

0.2

%tDCO

STOP recovery time

(Internal Reference Clock trimmed to 32 kHz)

tSTP_REC

-20

μs

Oscillator Monitor Failure Assert Frequency

fOMFA

200

kHz

Reset input pulse width, minimum input time

PWRSTL

2.0

tDCO_MIN

Startup from Reset

nRST

772

773

tDCO_MIN

Note:

40. Reference Frequency is factory trimmed

41. % deviation from target frequency, target frequency is fIREF_TRIM * (1000 + 2*MULT[6:0])

42. fDCO = 40 MHz, fIREF_TRIM = 32 kHz, MULT = $7D

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