MM912F634CV2AP datasheet(6/335 Pages) FREESCALE

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Pin Assignment

MM912F634 Pin Description

MM912F634

Freescale Semiconductor

2.1

MM912F634 Pin Description

The following table gives a brief description of all available pins on the MM912F634 package. Refer to the highlighted chapter for

detailed information.

Table 3. MM912F634 Pin Description

Pin #

Pin Name

Formal Name

Description

Not connected Pin

This pin is reserved for alternative function and should be left floating or connected

to GND.

EXTAL

MCU Oscillator Pin

EXTAL is one of the optional crystal/resonator driver and external clock pins. On

reset, all the device clocks are derived from the Internal Reference Clock. See

Section 4.33, “External Oscillator (S12SS12SCRGV1)".

XTAL

MCU Oscillator Pin

XTAL is one of the optional crystal/resonator driver and external clock pins. On

reset, all the device clocks are derived from the Internal Reference Clock. See

Section 4.33, “External Oscillator (S12SS12SCRGV1)".

TEST

MCU Test Pin

This input only pin is reserved for test. This pin has a pull-down device. The TEST

pin must be tied to EVSS in user mode.

PA5

MCU PA5 Pin

General purpose port A input or output pin 5. See Section 4.27, “Port Integration

Module (9S12I32PIMV1)"

PA4

MCU PA4 Pin

General purpose port A input or output pin 4. See Section 4.27, “Port Integration

Module (9S12I32PIMV1)".

PA3

MCU PA3 / SS Pin

General purpose port A input or output pin 3, shared with the SS signal of the

integrated SPI Interface. See Section 4.27, “Port Integration Module

(9S12I32PIMV1)".

PA2

MCU PA2 / SCK Pin

General purpose port A input or output pin 2, shared with the SCLK signal of the

integrated SPI Interface. See Section 4.27, “Port Integration Module

(9S12I32PIMV1)".

PA1

MCU PA1 / MOSI Pin

General purpose port A input or output pin 1, shared with the MOSI signal of the

integrated SPI Interface. See Section 4.27, “Port Integration Module

(9S12I32PIMV1)".

PA0

MCU PA0 / MISO Pin

General-purpose port A input or output pin 0, shared with the MISO signal of the

integrated SPI Interface. See Section 4.27, “Port Integration Module

(9S12I32PIMV1)".

EVSSX

MCU 5.0 V Ground Pin

Ground for the MCU 5.0 V power supply.

EVDDX

MCU 5.0 V Supply Pin

MCU 5.0 V - I/O buffer supply. See Section 4.26, “MM912F634 - MCU Die

Overview".

EVSS

MCU 2.5 V Ground Pin

Ground for the MCU 2.5 V power supply.

EVDD

MCU 2.5 V Supply Pin

MCU 2.5 V - MCU Core- and Flash power supply. See Section 4.26, “MM912F634

- MCU Die Overview".

VDD

Voltage Regulator

Output 2.5 V

+2.5 V main voltage regulator output pin. External capacitor (CVDD) needed. See

Section 4.4, “Power Supply".

VDDX

Voltage Regulator Output

5.0 V

+5.0 V main voltage regulator output pin. External capacitor (CVDDX) needed. See

Section 4.4, “Power Supply".

DGND

Digital Ground Pin

This pin is the device digital ground connection for the 5.0 V and 2.5 V logic. DGND,

LGND, and AGND are internally connected to PGND via a back to back diode.

VSENSE

Voltage Sense Pin

Battery voltage sense input. This pin can be connected directly to the battery line for

voltage measurements. The voltage present at this input is scaled down by an

internal voltage divider, and can be routed to the internal ADC via the analog

multiplexer.The pin is self-protected against reverse battery connections. An

external resistor (RVSENSE) is needed for protection(3). See Section 4.22, “Supply

Voltage Sense - VSENSE".

MM912F634CV2AP Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc

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