MM912F634CV2AP datasheet(94/335 Pages) FREESCALE

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Functional Description and Application Information

PWM Control Module (PWM8B2C)

MM912F634

Freescale Semiconductor

4.13.3.6

PWM Channel Period Registers (PWMPERx)

NOTE

Reads of this register return the most recent value written. Reads do not necessarily return

the value of the currently active period due to the double buffering scheme.

There is a dedicated period register for each channel. The value in this register determines the period of the associated PWM

channel.

The period registers for each channel are double buffered, so if they change while the channel is enabled, the change will NOT

take effect until one of the following occurs:

•

The effective period ends

•

The counter is written (counter resets to $00)

•

The channel is disabled

In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between.

If the channel is not enabled, then writes to the period register will go directly to the latches as well as the buffer.

See Section 4.13.4.2.3, “PWM Period and Duty"” for more information.

To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA, or SB) and multiply it

by the value in the period register for that channel:

•

Left aligned output (CAEx = 0)

•

PWMx Period = Channel Clock Period * PWMPERx Center Aligned Output (CAEx = 1)

•

PWMx Period = Channel Clock Period * (2 * PWMPERx)

For boundary case programming values, please refer to Section 4.13.4.2.7, “PWM Boundary Cases"”.

Table 119. PWM Channel Period Registers (PWMPERx)

Offset(85) 0x66/0x67

Access: User read/write

543

210

Bit 7

Bit 0

Reset

000

Note:

85. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

MM912F634CV2AP Datasheet(PDF) 94 Page - Freescale Semiconductor, Inc

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