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MM912F634CV2AP Datasheet(PDF) 89 Page - Freescale Semiconductor, Inc |
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MM912F634CV2AP Datasheet(HTML) 89 Page - Freescale Semiconductor, Inc |
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89 / 335 page ![]() Functional Description and Application Information PWM Control Module (PWM8B2C) MM912F634 Freescale Semiconductor 89 4.13.3 Register Descriptions This section describes in detail all the registers and register bits in the PWM module. Reserved bits within a register will always read as 0 and the write will be unimplemented. Unimplemented functions are indicated by shading the bit. 4.13.3.1 PWM Control Register (PWMCTL) Table 109. PWM Register Summary Name / Offset(79) 7 6 5 4 3 2 1 0 0x60 PWMCTL R CAE1 CAE0 PCLK1 PCLK0 PPOL1 PPOL0 PWME1 PWME0 W 0x61 PWMPRCLK R0 PCKB2 PCKB1 PCKB0 0 PCKA2 PCKA1 PCKA0 W 0x62 PWMSCLA R Bit 7 6 5 4 3 2 1 Bit 0 W 0x63 PWMSCLB R Bit 7 6 5 4 3 2 1 Bit 0 W 0x64 PWMCNT0 R Bit 7 6 5 4 3 2 1 Bit 0 W 000 00 000 0x65 PWMCNT1 R Bit 7 6 5 4 3 2 1 Bit 0 W 000 00 000 0x66 PWMPER0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x67 PWMPER1 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x68 PWMDTY0 R Bit 7 6 5 4 3 2 1 Bit 0 W 0x69 PWMDTY1 R Bit 7 6 5 4 3 2 1 Bit 0 W Note: 79. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. Table 110. PWM Control Register (PWMCTL) Offset(80) 0x60 Access: User read/write 76 543 210 R CAE1 CAE0 PCLK1 PCLK0 PPOL1 PPOL0 PWME1 PWME0 W Reset 0 000 00 00 Note: 80. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space. |
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