MM912F634CV2AP datasheet(93/335 Pages) FREESCALE

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Functional Description and Application Information

PWM Control Module (PWM8B2C)

MM912F634

Freescale Semiconductor

4.13.3.5

PWM Channel Counter Registers (PWMCNTx)

NOTE

Writing to the counter while the channel is enabled can cause an irregular PWM cycle to

occur.

Each channel has a dedicated 8-bit up/down counter, which runs at the rate of the selected clock source. The counter can be

read at any time without affecting the count or the operation of the PWM channel. In left aligned output mode, the counter counts

from 0 to the value in the period register - 1. In center aligned output mode, the counter counts from 0 up to the value in the period

Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of

both duty and period registers with values from the buffers, and the output to change according to the polarity bit. The counter is

also cleared at the end of the effective period (see Section 4.13.4.2.5, “Left Aligned Outputs"” and Section 4.13.4.2.6, “Center

Aligned Outputs"” for more details). When the channel is disabled (PWMEx = 0), the PWMCNTx register does not count. When

a channel becomes enabled (PWMEx = 1), the associated PWM counter starts at the count in the PWMCNTx register. For more

detailed information on the operation of the counters, see Section 4.13.4.2.4, “PWM Timer Counters"”.

Table 117. PWM Scale B Register (PWMSCLB)

Offset(83) 0x63

Access: User read/write

654321

Bit 7

Bit 0

Reset

000

00000

Note:

83. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 118. PWM Channel Counter Registers (PWMCNTx)

Offset(84) 0x64/0x65

Access: User read/write

543

210

Bit 7

Bit 0

000

Reset

000

Note:

84. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

MM912F634CV2AP Datasheet(PDF) 93 Page - Freescale Semiconductor, Inc