MM912F634CV2AP datasheet(100/335 Pages) FREESCALE

100 / 335 page

Functional Description and Application Information

PWM Control Module (PWM8B2C)

MM912F634

Freescale Semiconductor

100

4.13.4.2.3

PWM Period and Duty

NOTE

When forcing a new period or duty into effect immediately, an irregular PWM cycle can occur.

Depending on the polarity bit, the duty registers will contain the count of either the high time

or the low time.

Dedicated period and duty registers exist for each channel and are double buffered, so if they change while the channel is

enabled, the change will NOT take effect until one of the following occurs:

•

The effective period ends

•

The counter is written (counter resets to $00)

•

The channel is disabled

In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between.

If the channel is not enabled, then writes to the period and duty registers will go directly to the latches as well as the buffer.

A change in duty or period can be forced into effect “immediately” by writing the new value to the duty and/or period registers,

and then writing to the counter. This forces the counter to reset and the new duty and/or period values to be latched. In addition,

since the counter is readable, it is possible to know where the count is with respect to the duty value, and software can be used

to make adjustments

4.13.4.2.4

PWM Timer Counters

NOTE

To start a new “clean” PWM waveform without any “history” from the old waveform, writing

the channel counter (PWMCNTx) must happen prior to enabling the PWM channel

(PWMEx = 1).

Writing to the counter while the channel is enabled can cause an irregular PWM cycle to

occur.

Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source (see Section 4.13.4.1,

“PWM Clock Select"” for the available clock sources and rates). The counter compares to two registers, a duty register and a

period register as shown in Figure 26. When the PWM counter matches the duty register, the output flip-flop changes state,

causing the PWM waveform to also change state. A match between the PWM counter and the period register behaves differently

depending on what output mode is selected as shown in Figure 26 and described in Section 4.13.4.2.5, “Left Aligned Outputs"”

and Section 4.13.4.2.6, “Center Aligned Outputs"”.

Each channel counter can be read at anytime without affecting the count or the operation of the PWM channel.

Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of

both duty and period registers with values from the buffers, and the output to change according to the polarity bit. When the

channel is disabled (PWMEx = 0), the counter stops. When a channel becomes enabled (PWMEx = 1), the associated PWM

counter continues from the count in the PWMCNTx register. This allows the waveform to continue where it left off when the

channel is re-enabled. When the channel is disabled, writing “0” to the period register will cause the counter to reset on the next

selected clock.

Generally, writes to the counter are done prior to enabling a channel in order to start from a known state. However, writing a

counter can also be done while the PWM channel is enabled (counting). The effect is similar to writing the counter when the

channel is disabled, except that the new period is started immediately with the output set according to the polarity bit.

The counter is cleared at the end of the effective period (see Section 4.13.4.2.5, “Left Aligned Outputs"” and Section 4.13.4.2.6,

“Center Aligned Outputs"” for more details).

MM912F634CV2AP Datasheet(PDF) 100 Page - Freescale Semiconductor, Inc

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