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MM912F634CV2AP Datasheet(PDF) 61 Page - Freescale Semiconductor, Inc |
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MM912F634CV2AP Datasheet(HTML) 61 Page - Freescale Semiconductor, Inc |
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61 / 335 page ![]() Functional Description and Application Information Power Supply MM912F634 Freescale Semiconductor 61 Figure 18. Power Up / Down Sequence To avoid any critical behavior, it is essential to have the MCU Power On Reset (POR) active when the analog die reset (RESET_A) is not fully active. As the RESET_A circuity is supplied by VDDX, VDD needs to be below the POR threshold when VDDX is to low to guarantee RESET_A active (3;6). This is achieved with the following implementation. Power Up: • The VDD regulator is enabled after VDDX has reached the VLVRX threshold (1). • Once VDD reaches VLRV, the RESET_A is released (2). Power Down: • Once VDDX has reached the VLVRX threshold (4), the VDD regulator is disabled and the regulator output is actively pulled down to discharge any VDD capacitance (5). RESET_A is activated as well. • The active discharge guarantees VDD to be below POR level before VDDX discharges below critical level for the reset circuity. 5V VLBI / VLVI Normal Operating Range (not to scale) VLVRX VLVR VPOR_A RESET_A VDDX VDD VSUP VPOR_MCU VROVX VROX MCU_POR 1 4 5 6 2 MCU_POR 3 |
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