MM912F634CV2AP datasheet(76/335 Pages) FREESCALE

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Functional Description and Application Information

Wake-up / Cyclic Sense

MM912F634

Freescale Semiconductor

4.8.2.3

Wake-up Source Register (WSR)

Reading the WSR will clear the wake-up status bit(s). Writing will have no effect. The Wake-up Source Register (WSR) has to be

read after a wake-up condition, in order to execute a new STOP mode command. Two base clock cycles (fBASE) delays are

required between the WSR read and the MCR write.

Table 89. Wake-up Source Register (WSR)

Offset(70) 0x14

Access: User read

5432

FWU

LINWU

L5WU

L4WU

L3WU

L2WU

L1WU

L0WU

Note:

70. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 90. WSR - Register Field Descriptions

Field

Description

7 - FWU

Forced Wake-up - Wake-up caused by a forced wake-up

6 - LINWU

LIN Wake-up - Wake-up caused by a LIN wake-up

5 - L5WU

L5 Wake-up - Wake-up caused by a state change of the L6 Input

4 - L4WU

L4 Wake-up - Wake-up caused by a state change of the L5 Input

3 - L3WU

L3 Wake-up - Wake-up caused by a state change of the L4 Input

2 - L2WU

L2 Wake-up - Wake-up caused by a state change of the L3 Input

1 - L1WU

L1 Wake-up - Wake-up caused by a state change of the L2 Input

0 - L0WU

L0 Wake-up - Wake-up caused by a state change of the L1 Input

MM912F634CV2AP Datasheet(PDF) 76 Page - Freescale Semiconductor, Inc

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