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MM912F634CV2AP Datasheet(PDF) 52 Page - Freescale Semiconductor, Inc |
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MM912F634CV2AP Datasheet(HTML) 52 Page - Freescale Semiconductor, Inc |
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52 / 335 page ![]() Functional Description and Application Information MM912F634 - Analog Die Overview MM912F634 Freescale Semiconductor 52 4.2.3.1 Current Sense Module For device options with the current sense module not available, the following considerations are to be made. 4.2.3.1.1 Pinout considerations 4.2.3.1.2 Register Considerations The Current Sense Register must remain in default (0x00) state. The Conversion Control Register - Bit 9 must always be written 0. The Conversion Complete Register - Bit 9 must be ignored. The ADC Data Result Reg 9 must be ignored. Table 69. ISENSE - Pin Considerations PIN PIN name for option 1 New PIN name Comment 40 ISENSEL NC ISENSE feature not bonded and/or not tested. Connect PINs 40 and 41 (NC) to GND. 41 ISENSEH NC Offset Name 76 54 321 0 0x3C CSR R CSE 00 0 CCD CSGS Current Sense Register W 0x82 ACCR (hi) R CH15 CH14 0 CH12 CH11 CH10 CH9 CH8 ADC Conversion Ctrl Reg W 0x84 ACCSR (hi) R CC15 CC14 0 CC12 CC11 CC10 CC9 CC8 ADC Conv Complete Reg W 0x98 ADR9 (hi) R adr9 9 adr9 8 adr9 7 adr9 6 adr9 5 adr9 4 adr9 3 adr9 2 ADC Data Result Register 9 W 0x99 ADR9 (lo) R adr9 1 adr9 0 0 0 0 0 0 0 ADC Data Result Register 9 W |
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