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MM912F634CV2AP Datasheet(PDF) 91 Page - Freescale Semiconductor, Inc

Part # MM912F634CV2AP
Description  Integrated S12 Based Relay Driver with LIN
PDF  335 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MM912F634CV2AP Datasheet(HTML) 91 Page - Freescale Semiconductor, Inc

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Functional Description and Application Information
PWM Control Module (PWM8B2C)
MM912F634
Freescale Semiconductor
91
4.13.3.1.4
PWM Center Align Enable (CAEx)
NOTE
Write these bits only when the corresponding channel is disabled.
The CAEx bits select either center aligned outputs or left aligned output for both PWM channels. If the CAEx bit is set to a one,
the corresponding PWM output will be center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left
aligned. See Section 4.13.4.2.5, “Left Aligned Outputs"” and Section 4.13.4.2.6, “Center Aligned Outputs"” for a more detailed
description of the PWM output modes.
4.13.3.2
PWM Prescale Clock Select Register (PWMPRCLK)
NOTE
PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock pre-scale is
changed while a PWM signal is being generated, a truncated or stretched pulse can occur
during the transition.
This register selects the prescale clock source for clocks A and B independently.
Table 112. PWM Prescale Clock Select Register (PWMPRCLK)
Offset(81) 0x61
Access: User read/write
76
543
210
R0
PCKB2
PCKB1
PCKB0
0
PCKA2
PCKA1
PCKA0
W
Reset
0
000
00
00
Note:
81. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Table 113. PWMPRCLK - Register Field Descriptions
Field
Description
6–4
PCKB[2:0]
Prescaler Select for Clock B — Clock B is one of two clock sources which can be used for channel 1. These three bits
determine the rate of clock B, as shown in Table 114.
2–0
PCKA[2:0]
Prescaler Select for Clock A — Clock A is one of two clock sources which can be used for channel 0. These three bits
determine the rate of clock A, as shown in Table 115.
Table 114. Clock B Prescaler Selects
PCKB2
PCKB1
PCKB0
Value of Clock B
0
0
0
D2D clock
0
0
1
D2D clock / 2
0
1
0
D2D clock / 4
0
1
1
D2D clock / 8
1
0
0
D2D clock / 16
1
0
1
D2D clock / 32
1
1
0
D2D clock / 64
1
1
1
D2D clock / 128



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