MM912F634CV2AP datasheet(96/335 Pages) FREESCALE

96 / 335 page

Functional Description and Application Information

PWM Control Module (PWM8B2C)

MM912F634

Freescale Semiconductor

4.13.4

Functional Description

4.13.4.1

PWM Clock Select

There are four available clocks: clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These four clocks are based on

the D2D clock.

Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the D2D clock. Clock SA uses clock A as an

input and divides it further with a reloadable counter. Similarly, clock SB uses clock B as an input and divides it further with a

reloadable counter. The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in

increments of divide by 2. Similar rates are available for clock SB. Each PWM channel has the capability of selecting one of two

clocks, either the pre-scaled clock (clock A or B) or the scaled clock (clock SA or SB).

The block diagram in Figure 25 shows the four different clocks and how the scaled clocks are created.

4.13.4.1.1

Prescale

The input clock to the PWM prescaler is the D2D clock. The input clock can also be disabled when both PWM channels are

disabled (PWME1-0 = 0). This is useful for reducing power by disabling the prescale counter.

Clock A and clock B are scaled values of the input clock. The value is software selectable for both clock A and clock B and has

options of 1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, or 1/128 times the D2D clock. The value selected for clock A is determined by the

PCKA2, PCKA1, PCKA0 bits in the PWMPRCLK register. The value selected for clock B is determined by the PCKB2, PCKB1,

PCKB0 bits also in the PWMPRCLK register.

4.13.4.1.2

Clock Scale

The scaled A clock uses clock A as an input and divides it further with a user programmable value and then divides this by 2.

The scaled B clock uses clock B as an input and divides it further with a user programmable value and then divides this by 2.

The rates available for clock SA are software selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by

2. Similar rates are available for clock SB.

MM912F634CV2AP Datasheet(PDF) 96 Page - Freescale Semiconductor, Inc