MM912F634CV2AP datasheet(103/335 Pages) FREESCALE

103 / 335 page

Functional Description and Application Information

PWM Control Module (PWM8B2C)

MM912F634

Freescale Semiconductor

103

As an example of a center aligned output, consider the following case:

Clock Source = E, where E = 10 kHz (100 µs period)

PPOLx = 0

PWMPERx = 4

PWMDTYx = 1

PWMx Frequency = 10 kHz/8 = 1.25 kHz

PWMx Period = 800 µs

PWMx Duty Cycle = 3/4 *100% = 75%

Figure 30 shows the output waveform generated.

Figure 30. PWM Center Aligned Output Example Waveform

4.13.4.2.7

PWM Boundary Cases

Table 121 summarizes the boundary conditions for the PWM, regardless of the output mode (left aligned or center aligned).

4.13.5

Resets

The reset state of each individual bit is listed within the Section 4.13.3, “Register Descriptions"”, which details the registers and

their bit-fields. All special functions or modes which are initialized during or just following reset are described within this section.

•

The 8-bit up/down counter is configured as an up counter out of reset.

•

All the channels are disabled and all the counters do not count.

4.13.6

Interrupts

The PWM module has no Interrupts.

Table 121. PWM Boundary Cases

PWMDTYx

PWMPERx

PPOLx

PWMx Output

$00

(indicates no duty)

>$00

Always low

$00

(indicates no duty)

>$00

Always high

$00(87)

(indicates no period)

Always high

$00(87)

(indicates no period)

Always low

>= PWMPERx

Always high

Note:

87. Counter = $00 and does not count.

E = 100 µs

DUTY CYCLE = 75%

E = 100 µs

PERIOD = 800 µs

MM912F634CV2AP Datasheet(PDF) 103 Page - Freescale Semiconductor, Inc

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