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AS4C64M32MD2-25BCN Datasheet(PDF) 101 Page - Alliance Semiconductor Corporation |
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AS4C64M32MD2-25BCN Datasheet(HTML) 101 Page - Alliance Semiconductor Corporation |
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101 / 129 page  10. IDD Specification Parameters and Test Conditions 10.1 IDD Measurement Conditions The following definitions are used within the IDD measurement tables: LOW: VIN VIL(DC) MAX HIGH: VIN VIH(DC) MIN STABLE: Inputs are stable at a HIGH or LOW level SWITCHING: See Table 44 and Table 45. Table 44 — Definition of Switching for CA Input Signals Switching for CA CK (RISING) / CK# (FALLING) CK (FALLING) / CK# (RISING) CK (RISING) / CK# (FALLING) CK (FALLING) / CK# (RISING) CK (RISING) / CK# (FALLING) CK (FALLING) / CK# (RISING) CK (RISING) / CK# (FALLING) CK (FALLING) / CK# (RISING) Cycle N N+1 N+2 N+3 CS# HIGH HIGH HIGH HIGH CA0 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA1 HIGH HIGH HIGH LOW LOW LOW LOW HIGH CA2 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA3 HIGH HIGH HIGH LOW LOW LOW LOW HIGH CA4 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA5 HIGH HIGH HIGH LOW LOW LOW LOW HIGH CA6 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA7 HIGH HIGH HIGH LOW LOW LOW LOW HIGH CA8 HIGH LOW LOW LOW LOW HIGH HIGH HIGH CA9 HIGH HIGH HIGH LOW LOW LOW LOW HIGH NOTE 1 CS# must always be driven HIGH. NOTE 2 50% of CA bus is changing between HIGH and LOW once per clock for the CA bus. NOTE 3 The above pattern (N, N+1, N+2, N+3...) is used continuously during IDD measurement for IDD values that require SWITCHING on the CA bus. Table 45 — Definition of Switching for IDD4R Clock CKE CS# Clock Cycle Number Command CA0 - CA2 CA3-CA9 ALL DQ Rising HIGH LOW N Read_Rising HLH LHLHLHL L Falling HIGH LOW N Read_Falling LLL LLLLLLL L Rising HIGH HIGH N+1 NOP LLL LLLLLLL H Falling HIGH HIGH N+1 NOP HLH HLHLLHL L Rising HIGH LOW N+2 Read_Rising HLH HLHLLHL H Falling HIGH LOW N+2 Read_Falling HHH HHHHHHH H Rising HIGH HIGH N+3 NOP HHH HHHHHHH H Falling HIGH HIGH N+3 NOP HLH LHLHLHL L NOTE 1 Data strobe (DQS) is changing between HIGH and LOW every clock cycle. NOTE 2 The above pattern (N, N+1...) is used continuously during IDD measurement for IDD4R. Table 46 — Definition of Switching for IDD4W Clock CKE CS# Clock Cycle Number Command CA0 - CA2 CA3-CA9 ALL DQ Rising HIGH LOW N Write_Rising HLH LHLHLHL L Falling HIGH LOW N Write_Falling LLL LLLLLLL L Rising HIGH HIGH N+1 NOP LLL LLLLLLL H Falling HIGH HIGH N+1 NOP HLH HLHLLHL L Rising HIGH LOW N+2 Write_Rising HLL HLHLLHL H Falling HIGH LOW N+2 Write_Falling HHH HHHHHHH H Rising HIGH HIGH N+3 NOP HHH HHHHHHH H Falling HIGH HIGH N+3 NOP HLH LHLHLHL L NOTE 1 Data strobe (DQS) is changing between HIGH and LOW every clock cycle. NOTE 2 Data masking (DM) must always be driven LOW. NOTE 3 The above pattern (N, N+1...) is used continuously during IDD measurement for IDD4W. AS4C64M32MD2-25BCN AS4C128M16MD2-25BCN Confidential - 101/129 - Rev.1.0 July 2016 |
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