MM912F634CV2AP datasheet(207/335 Pages) FREESCALE

207 / 335 page

Functional Description and Application Information

Background Debug Module (S12SBDMV1)

MM912F634

Freescale Semiconductor

207

Figure 67 shows a SYNC command being issued after a READ_BYTE, which aborts the READ_BYTE command. Note that, after

the command is aborted, a new command could be issued by the host computer. Figure 67 does not represent the signals in a

true timing scale

Figure 67. ACK Abort Procedure at the Command Level

Figure 68 shows a conflict between the ACK pulse and the SYNC request pulse. This conflict could occur if a POD device is

connected to the target BKGD pin and the target is already in debug active mode. Consider that the target CPU is executing a

pending BDM command at the exact moment the POD is being connected to the BKGD pin. In this case, an ACK pulse is issued

along with the SYNC command. In this case, there is an electrical conflict between the ACK speedup pulse and the SYNC pulse.

Since this is not a probable situation, the protocol does not prevent this conflict from happening.

NOTE

This information is being provided so that the MCU integrator will be aware that such a

conflict could occur.

Figure 68. ACK Pulse and SYNC Request Conflict

READ_BYTE

READ_STATUS

BKGD Pin

Memory Address

New BDM Command

Host

Target

Host

Target

Host

Target

SYNC Response

From the Target

(Out of Scale)

BDM Decode

and Starts to Execute

the READ_BYTE Command

READ_BYTE CMD is Aborted

by the SYNC Request

(Out of Scale)

BDM Clock

(Target MCU)

Target MCU

Drives to

BKGD Pin

16 Cycles

Speedup Pulse

High-impedance

Host

Drives SYNC

To BKGD Pin

ACK Pulse

Host SYNC Request Pulse

At Least 128 Cycles

Electrical Conflict

Host and

Target Drive

to BKGD Pin

MM912F634CV2AP Datasheet(PDF) 207 Page - Freescale Semiconductor, Inc

MM912F634CV2AP Datasheet(HTML) 207 Page - Freescale Semiconductor, Inc

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