MM912F634CV2AP datasheet(203/335 Pages) FREESCALE

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Functional Description and Application Information

Background Debug Module (S12SBDMV1)

MM912F634

Freescale Semiconductor

203

pin. Internal glitch detect logic requires the pin be driven high no later that eight target clock cycles after the falling edge for a

logic 1 transmission.

Since the host drives the high speedup pulses in these two cases, the rising edges look like digitally driven signals.

Figure 62. BDM Host-to-Target Serial Bit Timing

The receive cases are more complicated. Figure 63 shows the host receiving a logic 1 from the target system. Since the host is

asynchronous to the target, there is up to one clock-cycle delay from the host-generated falling edge on BKGD to the perceived

start of the bit time in the target. The host holds the BKGD pin low long enough for the target to recognize it (at least two target

clock cycles). The host must release the low drive before the target drives a brief high speedup pulse seven target clock cycles

after the perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it started the bit time.

Figure 63. BDM Target-to-Host Serial Bit Timing (Logic 1)

Target Senses Bit

10 Cycles

Synchronization

Uncertainty

BDM Clock

(Target MCU)

Host

Transmit 1

Host

Transmit 0

Perceived

Start of Bit Time

Earliest

Start of

Next Bit

High-impedance

Earliest

Start of

Next Bit

R-C Rise

10 Cycles

Host Samples

BKGD Pin

Perceived

Start of Bit Time

BKGD Pin

BDM Clock

(Target MCU)

Host

Drive to

BKGD Pin

Target System

Speedup

Pulse

High-impedance

MM912F634CV2AP Datasheet(PDF) 203 Page - Freescale Semiconductor, Inc

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