Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

Preview PDF HTML

MM912F634CV2AP Datasheet(PDF) 199 Page - Freescale Semiconductor, Inc

Part # MM912F634CV2AP
Description  Integrated S12 Based Relay Driver with LIN
PDF  335 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MM912F634CV2AP Datasheet(HTML) 199 Page - Freescale Semiconductor, Inc

Back Button MM912F634CV2AP Datasheet HTML 195Page - Freescale Semiconductor, Inc MM912F634CV2AP Datasheet HTML 196Page - Freescale Semiconductor, Inc MM912F634CV2AP Datasheet HTML 197Page - Freescale Semiconductor, Inc MM912F634CV2AP Datasheet HTML 198Page - Freescale Semiconductor, Inc MM912F634CV2AP Datasheet HTML 199Page - Freescale Semiconductor, Inc MM912F634CV2AP Datasheet HTML 200Page - Freescale Semiconductor, Inc MM912F634CV2AP Datasheet HTML 201Page - Freescale Semiconductor, Inc MM912F634CV2AP Datasheet HTML 202Page - Freescale Semiconductor, Inc MM912F634CV2AP Datasheet HTML 203Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 199 / 335 page
background image
Functional Description and Application Information
Background Debug Module (S12SBDMV1)
MM912F634
Freescale Semiconductor
199
4.30.4.3
BDM Hardware Commands
Hardware commands are used to read and write target system memory locations and to enter active background debug mode.
Target system memory includes all memory that is accessible by the CPU such as on-chip RAM, Flash, I/O and control registers.
Hardware commands are executed with minimal or no CPU intervention and do not require the system to be in active BDM for
execution, although, they can still be executed in this mode. When executing a hardware command, the BDM sub-block waits for
a free bus cycle so that the background access does not disturb the running application program. If a free cycle is not found within
128 clock cycles, the CPU is momentarily frozen so that the BDM can steal a cycle. When the BDM finds a free cycle, the
operation does not intrude on normal CPU operation provided that it can be completed in a single cycle. However, if an operation
requires multiple cycles the CPU is frozen until the operation is complete, even though the BDM found a free cycle.
The BDM hardware commands are listed in Table 256.
The READ_BD and WRITE_BD commands allow access to the BDM register locations. These locations are not normally in the
system memory map but share addresses with the application in memory. To distinguish between physical memory locations that
share the same address, BDM memory resources are enabled just for the READ_BD and WRITE_BD access cycle. This allows
the BDM to access BDM locations unobtrusively, even if the addresses conflict with the application memory map.
If ACK pulse is enabled, an ACK pulse will occur when data is ready for transmission for all BDM READ commands and will occur
after the write is complete for all BDM WRITE commands
Table 256. Hardware Commands
Command
Opcode
(hex)
Data
Description
BACKGROUND
90
None
Enter background mode if firmware is enabled. If enabled, an ACK will be issued when
the part enters active background mode.
ACK_ENABLE
D5
None
Enable Handshake. Issues an ACK pulse after the command is executed.
ACK_DISABLE
D6
None
Disable Handshake. This command does not issue an ACK pulse.
READ_BD_BYTE
E4
16-bit address
16-bit data out
Read from memory with standard BDM firmware lookup table in map.
Odd address data on low byte; even address data on high byte.
READ_BD_WORD
EC
16-bit address
16-bit data out
Read from memory with standard BDM firmware lookup table in map.
Must be aligned access.
READ_BYTE
E0
16-bit address
16-bit data out
Read from memory with standard BDM firmware lookup table out of map.
Odd address data on low byte; even address data on high byte.
READ_WORD
E8
16-bit address
16-bit data out
Read from memory with standard BDM firmware lookup table out of map. Must be
aligned access.
WRITE_BD_BYTE
C4
16-bit address
16-bit data in
Write to memory with standard BDM firmware lookup table in map.
Odd address data on low byte; even address data on high byte.
WRITE_BD_WORD
CC
16-bit address
16-bit data in
Write to memory with standard BDM firmware lookup table in map.
Must be aligned access.
WRITE_BYTE
C0
16-bit address
16-bit data in
Write to memory with standard BDM firmware lookup table out of map.
Odd address data on low byte; even address data on high byte.
WRITE_WORD
C8
16-bit address
16-bit data in
Write to memory with standard BDM firmware lookup table out of map.
Must be aligned access.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com