MM912F634CV2AP datasheet(195/335 Pages) FREESCALE

195 / 335 page

Functional Description and Application Information

Background Debug Module (S12SBDMV1)

MM912F634

Freescale Semiconductor

195

4.30.3.2.1

BDM Status Register (BDMSTS)

4.30.3.2.2

BDM Status Register (BDMSTS)

NOTE

When BDM is made active, the CPU stores the content of its CCR register in the BDMCCR

0xD0, which is the reset value of the CCR register in this CPU mode. Out of reset in all other

modes, the BDMCCR register is read zero.

Read: All modes through BDM operation when not secured

Write: All modes through BDM operation when not secured, but subject to the following:

— ENBDM should only be set via a BDM hardware command if the BDM firmware commands are needed. (This does

not apply in special single chip mode).

— BDMACT can only be set by BDM hardware upon entry into BDM. It can only be cleared by the standard BDM

firmware lookup table upon exit from BDM active mode.

— All other bits, while writable via BDM hardware or standard BDM firmware write commands, should only be altered

by the BDM hardware or standard firmware lookup table as part of BDM command execution.

0x3_FF08

BDMPPR

BPAE

000

BPP3

BPP2

BPP1

BPP0

0x3_FF09

Reserved

0000000

0x3_FF0A

Reserved

0000000

0x3_FF0B

Reserved

0000000

Table 251. Register Global Address 0x3_FF01

765

43210

ENBDM

BDMACT

SDV

TRACE

UNSEC

Reset

Special Single-Chip Mode

0(165)

0(166)

All Other Modes

Note:

165. ENBDM is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but fully erased

(Flash). This is because the ENBDM bit is set by the standard firmware before a BDM command can be fully transmitted and executed.

166. UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased, else it is 0

and can only be read if not secure (see also bit description).

Figure 60. BDM Register Summary (continued)

Global

Address

Name

Bit 7

Bit 0

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