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MM912F634CV2AP Datasheet(PDF) 192 Page - Freescale Semiconductor, Inc |
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MM912F634CV2AP Datasheet(HTML) 192 Page - Freescale Semiconductor, Inc |
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192 / 335 page  Functional Description and Application Information Background Debug Module (S12SBDMV1) MM912F634 Freescale Semiconductor 192 4.30 Background Debug Module (S12SBDMV1) 4.30.1 Introduction This section describes the functionality of the background debug module (BDM) sub-block of the HCS12S core platform. The background debug module (BDM) sub-block is a single-wire, background debug system implemented in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD pin. The BDM has enhanced capability for maintaining synchronization between the target and host while allowing more flexibility in clock rates. This includes a sync signal to determine the communication rate and a handshake signal to indicate when an operation is complete. The system is backwards compatible to the BDM of the S12 family with the following exceptions: • TAGGO command not supported by S12SBDM • External instruction tagging feature is part of the DBG module • S12SBDM register map and register content modified • Family ID readable from firmware ROM at global address 0x3_FF0F (value for devices with HCS12S core is 0xC2) • Clock switch removed from BDM (CLKSW bit removed from BDMSTS register) 4.30.1.1 Features The BDM includes these distinctive features: • Single-wire communication with host development system • Enhanced capability for allowing more flexibility in clock rates • SYNC command to determine communication rate • GO_UNTIL(169) command • Hardware handshake protocol to increase the performance of the serial communication • Active out of reset in special single chip mode • Nine hardware commands using free cycles, if available, for minimal CPU intervention • Hardware commands not requiring active BDM • 14 firmware commands execute from the standard BDM firmware lookup table • Software control of BDM operation during wait mode • When secured, hardware commands are allowed to access the register space in special single chip mode, if the Flash and EEPROM erase tests fail. • Family ID readable from firmware ROM at global address 0x3_FF0F (value for devices with HCS12S core is 0xC2) • BDM hardware commands are operational until system stop mode is entered 4.30.1.2 Modes of Operation BDM is available in all operating modes but must be enabled before firmware commands are executed. Some systems may have a control bit that allows suspending the function during background debug mode. 4.30.1.2.1 Regular Run Modes All of these operations refer to the part in run mode and not being secured. The BDM does not provide controls to conserve power during run mode. • Normal modes General operation of the BDM is available and operates the same in all normal modes. • Special single chip mode In special single chip mode, background operation is enabled and active out of reset. This allows programming a system with blank memory. |
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