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MM912F634CV2AP Datasheet(PDF) 194 Page - Freescale Semiconductor, Inc |
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MM912F634CV2AP Datasheet(HTML) 194 Page - Freescale Semiconductor, Inc |
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194 / 335 page  Functional Description and Application Information Background Debug Module (S12SBDMV1) MM912F634 Freescale Semiconductor 194 4.30.2 External Signal Description A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate with the BDM system. During reset, this pin is a mode select input which selects between normal and special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the background debug mode. The communication rate of this pin is based on the DCO clock or external reference clock depending on the configuration selected (please refer to the S12S_CRG Block Guide for more details) which gets divided by five. Hence the BDM serial interface clock is always DCO clock divided by five after reset in to Special Single Chip mode which is about 6.4 MHz. After reset the BDM communication rate can be modified either via BDM command or CPU user code. When modifying the DCO clock please make sure that the communication rate is adapted accordingly and a communication timeout (BDM soft reset) has occurred. 4.30.3 Memory Map and Register Definition 4.30.3.1 Module Memory Map Table 250 shows the BDM memory map when BDM is active. 4.30.3.2 Register Descriptions A summary of the registers associated with the BDM is shown in Figure 60. Registers are accessed by host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands. Table 250. BDM Memory Map Global Address Module Size (Bytes) 0x3_FF00–0x3_FF0B BDM registers 12 0x3_FF0C–0x3_FF0E BDM firmware ROM 3 0x3_FF0F Family ID (part of BDM firmware ROM) 1 0x3_FF10–0x3_FFFF BDM firmware ROM 240 Figure 60. BDM Register Summary Global Address Register Name Bit 7 6 5 4 3 2 1 Bit 0 0x3_FF00 Reserved R X X XXXX 0 0 W 0x3_FF01 BDMSTS R ENBDM BDMACT 0 SDV TRACE 0 UNSEC 0 W 0x3_FF02 Reserved R X X XXXXXX W 0x3_FF03 Reserved R X X XXXXXX W 0x3_FF04 Reserved R X X XXXXXX W 0x3_FF05 Reserved R X X XXXXXX W 0x3_FF06 BDMCCR R CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0 W 0x3_FF07 Reserved R 0000000 0 W |
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