BQ76PL455APFCT datasheet(22/125 Pages) TI1

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bq76PL455A

SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

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7.3.1.1.8

VM Charge Pump

The included internal-charge pump is for biasing the Analog Front End (AFE) and other analog circuits. It

requires an external flying capacitor connected between the CHP and CHM pins plus a storage capacitor on pin

VM to generate a rail of –5 V for internal use. The charge pump (VM) is always on in IDLE and off in

SHUTDOWN. VM requires the oscillator to be running and stable and does not start until the other supplies are

above their POR thresholds. The VM charge pump will start ramping at the start of the WAKEUP tone on COMH.

7.3.2 Analog Front End (AFE)/Level Shifter

The bq76PL455A AFE allows monitoring of up to 16 cells. Provided for this purpose are seventeen VSENSE

inputs, labeled VSENSE0 through VSENSE16. The programming for bq76PL455A can be set to sample all, or a

subset, of the connected cells. Sampling always begins at the highest-selected cell and finishes with the lowest-

selected cell. During measurement, the AFE selects the cell addressed by the logic block and level-shift the

sensed cell voltage with a gain of 1 down to the ground-referred OUT1 pin. The output of the AFE (OUT1) has a

See section '' for component selection.

The analog output of the AFE connects to OUT1 through an internal 1.2-k

Ω series resistor. Connect OUT1

externally to OUT2. At this external connection between the AFE and the ADC, the requirement is to place an

external filter capacitor to form an RC filter to reduce noise bandwidth. A filter capacitor will increase the settling

time of the signal presented to the ADC input. A trade-off can be made between ADC sample time, filtering, and

accuracy. The AFE output must settle to within < 1/4 of the ADC LSB for best measurement accuracy.

7.3.3 ADC

The ADC in the bq76PL455A is a 14-bit Successive Approximation Register (SAR) ADC. It has a fixed

conversion (hold) time of 3.44 µs, with a user-selectable sample interval or period between conversions. The

user-selectable sample interval determines the acquisition (tracking) settling time between conversions, used

mostly to allow the input capacitor on OUT1 to settle between conversions, and to allow for internal settling.

The ADC input mux on the digital die allows it to connect to the following:

•

The AFE (analog die) mux output on OUT1 which measures:

–

Up to 16 cell voltage channels

–

The VMODULE voltage

–

The internal temperature of the analog die

–

The REF2 analog die reference

–

The VM (–5V) charge pump generated voltage supply on the analog die

•

Measurement channels on the digital die:

–

The 8 AUX input channels

–

The VDD18 1.8-V voltage supply on the digital die

–

The internal temperature of the digital die

The ADC can be set up to take single samples or multiple samples in one of two averaging modes. This

selection is made using OVERSMPL[CMD_OVS_CYCLE].

7.3.3.1 Channel Selection Registers

Program channels for measurement by setting bits in the CHANNELS and NCHAN registers. Each channel can

be set up for measurement individually. User programmable correction factors are available for cell and AUX

channels. Conversion times are individually user programmable for different types of inputs (that is, cells, AUX,

and internal measurements).

The NCHAN register sets the number of VSENSE channels (cell inputs) for use by the device. Unused channels

are dropped consecutively starting from channel 16. Set this register for the number of cells used, that is, for 14

cells, program 0x0E. This register also sets mask cell overvoltage and undervoltage faults for unused channels,

and turns off the UV and OV comparators associated with the channel. The idle channel (the channel the mux

rests on between sample intervals) is set to the value in this register. This allows the OUT1 pin to hold the filter

capacitor at the voltage, which will be sampled first on the next cycle.

BQ76PL455APFCT Datasheet(PDF) 22 Page - Texas Instruments

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