BQ76PL455APFCT datasheet(45/125 Pages) TI1

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bq76PL455A

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SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

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Device Functional Modes (continued)

Note that this sequence is the same regardless of the reset source—POR, soft reset, wake tone received from

the part below.

1. External NPN regulator circuit turns on. VP, VDIG, (and VIO if connected to VP) begin to ramp up. If VIO is

supplied by an external source (such as the microcontroller I/O power supply), then VIO must be stable and

greater than its POR threshold.

2. Once VDIG reaches its POR threshold, the internal 1.8 V (internal digital supply VDD) regulator begins to

ramp up. Once VDIG reaches the POR threshold, VREF and the internal 1.8 V supply (VDD18) start up. The

reference for the VDD (1.8 V) supply is VREF, so it will not reach its final operating voltage until VREF

reaches its final voltage.

3. Once VP, VDIG, VIO, and VDD all reach their POR thresholds, the oscillator starts.

4. Once the oscillator is running, the Finite State Machine (FSM) starts up and begins sending the wake tone

out of the high-side interface (COMMH±).

5. The FSM in turn waits approximately 10 µs for the EEPROM to be ready.

6. All system registers will be loaded from EEPROM.

7. Relevant information will be propagated to the Analog die registers, except regulator power down.

8. If GPIO addressing is enabled (DEVCONFIG[ADDR_SEL] = 0), the GPIO[4:0] pins are sampled to determine

the device's communication address and recorded in ADDR.

9. Sample the internal Digital-die temperature channel. This pre-loads the value, so temperature-based

calibration will function properly. No other channels will be sampled during initialization and faults will not be

generated from them until after they are sampled.

10. Clear any masked faults that could have occurred. This includes clearing threshold-based faults that are

masked by their threshold.

11. Begin monitoring for UART communications.

12. Initialize Analog die faults. (Continue sequencing in parallel; do not wait for the following sub-sequence to

complete.)

(a) Wait until no VM fault is reported from Analog die or the user writes '1' to STATUS[SYS_INIT].

(b) Enable all Analog die fault registers.

13. Wait for wakeup tone to complete.

14. Begin monitoring for differential communications.

15. Once the FAULT_SYS[SYS_RESET] fault is cleared by the host microcontroller, turn off the external NPN-

regulator circuit if the regulator is disabled (that is, DEVCONFIG[REG_DISABLE] = 1).

While the system initialization sequence above is in progress (while SYS_INIT reads '1'), many faults will not

report properly and sampling commands may not function properly. Also, note that aborting the initialization

sequence (by writing '1' to SYS_INIT) may cause the reporting of erroneous faults and sampling of Analog

channels to report invalid results until the VM voltage is up and stable.

Additionally, there is a delay associated with the enabling of the UART communications and a delay associated

with the completion of the initialization process once the VM fault clears (or the user aborts the initialization

sequence).

BQ76PL455APFCT Datasheet(PDF) 45 Page - Texas Instruments

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