BQ76PL455APFCT datasheet(71/125 Pages) TI1

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bq76PL455A

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SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

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BIT

NAME

DESCRIPTION

[2:0]

CMD_OVSMP

These bits set the number of times each ADC converted value will be averaged before

being stored. Each converted signal will be sampled the requested number of times,

averaged, and the results convergent rounded to 16 bits.

= 0

= 1

= 2

= 3

= 4

= 5

= 6–7

Single sample (no averaging)

2 samples are averaged.

4 samples are averaged.

8 samples are averaged.

16 samples are averaged.

32 samples are averaged.

Reserved, do not use this value.

7.6.3.5 ADDR 0x0A (10) Device Address

BIT

NAME

DESCRIPTION

[7:5]

RSVD

Reserved — always write as zero.

[4:0]

DEV_ADDR

These bits set the device address that the device will respond. These bits can only be written when

AUTO_ADDRESS is set to 1. Otherwise, writes to these bits are ignored. The address may also be stored

and loaded from EEPROM or using GPIO bits. See text for details.

7.6.3.6 GROUP_ID 0x0B (11) Group ID

BIT

NAME

DESCRIPTION

[7:4]

RSVD

Reserved — always write as zero.

[3:0]

GROUP_ID

These bits set the lower 4 bits of the group identifier that the device will respond to for Group Broadcast

requests. The upper 4 bits of the group identifier are fixed at 0 and cannot be changed.

7.6.3.7 DEV_CTRL 0x0C (12) Device Control

BIT

NAME

DESCRIPTION

[7]

SOFT_RESET

Writing a '1' will return the device to its reset state, causing it to rerun its initialization sequence. This bit is

self-clearing and will always return '0' when read.

[6]

PWRDN

Writing a '1' will cause the device to shut down. This is usually broadcast to the entire stack of ICs to shut

down all of the bq76PL455A devices at the same time.

[5]

STACK_WAKE

Writing a '1' will cause a wakeup tone to be sent from the high-side communication interface to the next

device up the stack.

Note that setting this bit blocks communication to devices higher in the stack until the wakeup tone

sequence is complete. The time it takes to complete the stack wake sequence is dependent on the state

and number of devices in the stack.

This bit is self-clearing and will return '1' while a wakeup tone is in process, and '0' after it has completed.

[4]

WRITE_EEPROM

Writing a '1' while MAGIC1 is set to 0x8C2DB194 and MAGIC2 is set to 0xA375E60F causes the EEPROM

to save (be programmed with) the current register values.

This bit is self-clearing and will return '1' while the programming cycle is in progress, and '0' after the

programming cycle is complete. This bit should not be written while a programming cycle is in progress.

Normal EEPROM burns require COMM_PD_PER >= 3. For COMM_PD_PER settings smaller than this,

the user should have the device perform the following steps:

Set CCNT_RST_OFF = 1

Set COMM_TIM_CNT = 0x1000

Burn as normal

Do not write to registers while a programming cycle is in progress.

Do not shut down the device while a programming cycle is in progress.

[3]

AUTO_ADDRESS

If ADDR_SEL = 0, writing a '1' will cause the device to sample the GPIO pins and store the resulting value

in DEV_ADDR.

If ADDR_SEL = 1, writing a '1' will cause the device to enter auto addressing mode.

When ADDR_SEL = 1, this bit is self-clearing and will be set to '0' after the next frame is received, even if

that frame does not set DEV_ADDR.

When ADDR_SEL = 0 this bit is self-clearing and will always read 0.

BQ76PL455APFCT Datasheet(PDF) 71 Page - Texas Instruments

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