BQ76PL455APFCT datasheet(72/125 Pages) TI1

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bq76PL455A

SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

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BIT

NAME

DESCRIPTION

[2:0]

RSVD

Reserved — always write as zero

7.6.3.8 NCHAN 0x0D (13) Number of Channels

BIT

NAME

DESCRIPTION

[7:5]

RSVD

Reserved — always write as zero.

[4:0]

NUM_CHAN

This register sets the number of VSENSE channels (battery inputs) that will be used by the device. Unused

channels are dropped consecutively starting from channel 16.

The idle channel (the channel the MUX "rests" on between sample intervals) is set to this value.

A setting of 0 is not recommended. If 0 is set, the idle channel = VSENSE1.

This value masks cell overvoltage and undervoltage faults for unused channels and turns off the

comparators associated with the channel.

Values greater than 16 are reserved and should not be used.

7.6.3.9 DEVCONFIG 0x0E (14) Device Configuration

BIT

NAME

DESCRIPTION

[7:6]

Reserved

These bits must always be set to 0.

[5]

REG_DISABLE

0 = Internal regulator (NPN drive for VP/VDIG) is enabled. This is the normal operating mode.

1 = Internal regulator (NPN drive) is disabled. In this case, the bq76PL455A VP, VDIG, and VIO must be

externally supplied. REG_DISABLE = 1 is typically used only for some system diagnostic tests.

Regardless of the state of this bit, the regulator will always be enabled while FAULT_SYS[SYS_RESET]

= 1.

[4]

ADDR_SEL

0 = Address will be set using the GPIO inputs.

1 = Address will be set using auto addressing.

Note: Changing this bit will not change the current device address.

[3:2]

COMP_CONFIG

0 = Overvoltage (OV) and undervoltage (UV) comparators are enabled.

1 = OV comparators are enabled, UV comparators are disabled.

2 = Comparators are disabled.

3 = Reserved

[1]

COMP_HYST_EN

0 = Comparator hysteresis is disabled.

1 = Comparator hysteresis is enabled.

[0]

UNLATCHED_FAULT

0 = Faults are latched and write fault register to clear.

1 = Faults are unlatched and clear automatically.

This setting only applies to some fault registers. See individual fault register descriptions for details.

The UNLATCHED_FAULT bit should only be changed while no fault bits are set (= 1). The

latched/unlatched status of fault bits is undefined when the UNLATCHED_FAULT bit is changed while a

fault bit = 1.

7.6.3.10 PWRCONFIG (0x0F) (15) Power Configuration

BIT

NAME

DESCRIPTION

[7]

AFE_PCTL

It is strongly recommended this bit be set to 1.

Cell voltage sampling will be delayed by 100 µs every time sampling is requested, regardless of whether

or not the AFE was already powered up. This provides time for the AFE to power up and ensures that

the sampling synchronization is maintained between multiple devices.

Changes to this register may not take effect until after the next AFE sample is taken.

[6:0]

RSVD

Reserved — always write as zero.

7.6.3.11 COMCONFIG 0x10–11 (16–17) Communications Configuration

BIT

NAME

DESCRIPTION

[15:14]

RSVD

Reserved — always write/read as zero.

BQ76PL455APFCT Datasheet(PDF) 72 Page - Texas Instruments

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