BQ76PL455APFCT datasheet(86/125 Pages) TI1

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bq76PL455A

SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

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BIT

NAME

DESCRIPTION

[2:1]

RSVD

Reserved — always write/read as zero

[0]

STK_FAULT_ERR_MSK

0 = Do not mask this fault.

1 = Mask this fault.

Masked STK_FAULT_ERR is not cleared during initialization. As a result, there is an

approximately 5-µs window at startup where, if the high-side fault receiver detects more than

four falling edges, STK_FAULT_ERR will be set even though it is masked.

(1)

If the SYS_RESET_MSK is set to 1, this setting should be burned to EEPROM in order to provide useful information.

7.6.3.38 MASK_SYS 0x6A (106) System Fault Masks

BIT

NAME

DESCRIPTION

[7]

SYS_RESET_MSK(1)

For each of these bits:

0 = Do not mask this fault.

1 = Mask this fault.

[6]

COMM_TIMEOUTMSK

[5]

RSVD

Reserved — always write/read as zero

[4]

INT_TEMP_FAULT_MSK

For each of these bits:

0 = Do not mask this fault.

1 = Mask this fault.

[3]

VDIG_FAULT_MSK

[2]

VM_FAULT_MSK

[1]

VP_FAULT_MSK

[0]

VP_CLAMP_MSK

7.6.3.39 MASK_DEV 0x6B–6C (107–108) Chip Fault Masks

BIT

NAME

DESCRIPTION

[15]

USER_CKSUM_MSK

For each of these bits:

0 = Do not mask this fault.

1 = Mask this fault.

[14]

FACT_CKSUM_MSK

[13]

ANALOG_FERR_MSK

[12:0]

RSVD

Reserved — always write/read as zero

7.6.3.40 FO_CTRL 0x6E–6F (110–111) Fault Output Control

BIT

NAME

DESCRIPTION

[15]

UV_FAULT_OUT

For each of these bits:

0 = Do not include these faults in the fault output.

1 = Include these faults in the fault output.

[14]

OV_FAULT_OUT

[13]

AUXUV_FAULT_OUT

[12]

AUXOV_FAULT_OUT

[11]

CMPUV_FAULT_OUT

[10]

CMPOV_FAULT_OUT

[9]

COMM_FAULT_OUT

[8]

SYS_FAULT_OUT

[7]

CHIP_FAULT_OUT

[6]

GPI_FAULT_OUT

[5:0]

RSVD

Reserved — always write/read as zero

BQ76PL455APFCT Datasheet(PDF) 86 Page - Texas Instruments

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