BQ76PL455APFCT datasheet(83/125 Pages) TI1

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bq76PL455A

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SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

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BIT

NAME

DESCRIPTION

(1)

COMM_CLEAR causes STOP_ERR and COMM_CLEAR on base device and ABORT_L on the chips higher in the stack.

COMP_ERR_L, COMP_FLT_L, and EDGE_ERR_L faults do not occur on the base device in a stack configuration. See Protocol

Description section for more details.

[11]

EDGE_ERR_H

Write '1': Reset the fault condition.

Write '0': No effect

Read '1': A falling edge was not detected on the high-side interface by the 4th bit.

[10]

EDGE_ERR_L

Write '1': Reset the fault condition.

Write '0': No effect

Read '1': A falling edge was not detected on the low-side interface by the 4th bit.

[9]

ABORT_H

Write '1': Reset the fault condition.

Write '0': No effect

Read '1': A framing bit with value "1" was detected on the high-side differential interface.

A data byte was stopped and ignored. If this occurs on the high-side interface, it is always due to a

communication problem. Sending COMM_RESET or COMM_CLEAR to the UART interface on the

bottom chip will cause this fault on the low-side interface.

When it occurs on the high side, it may have caused this chip to fail to return its frame in a

broadcast or group response (although the microcontroller should already have detected this

before this bit was read).

[8]

ABORT_L(1)

Write '1': Reset the fault condition.

Write '0': No effect

Read '1': A framing bit with value "1" was detected on the low-side differential interface.

A data byte was stopped and ignored. ABORT_L also reads "1" on devices in a stack when a

COMM_RESET or COMM_CLEAR is sent to the UART interface on the base device of a stack.

[7]

CRC_FAULT_H

Write '1': Reset the fault condition.

Write '0': No effect

Read '1': A CRC fault has been detected on the high-side interface.

The frame was discarded. If it occurs on the high side, it may have caused this chip to fail to return

its frame in a broadcast or group response.

[6]

CRC_FAULT_L

Write '1': Reset the fault condition.

Write '0': No effect

Read '1': A CRC fault has been detected on the low-side interface (either single-ended UART or

differential VBUS).

The frame was discarded.

[5]

FRAME_ERR

Write '1': Reset the fault condition.

Write '0': No effect

Read '1': A framing error has been detected.

This indicates that the chip received a start of frame on the differential communications interface

before it had completed the prior frame.

[4]

RSVD

Reserved — always read as zero

[3]

STOP_ERR(1)

Write '1': Reset the fault condition.

Write '0': No effect

Read '1': The UART receiver detected an invalid stop bit on the single-ended low-side interface.

This error only appears on chips using the UART interface. COMM_CLEAR and COMM_RESET

will also cause this fault.

This error is specific to the UART interface.

[2:1]

RSVD

Reserved — always read as zero

[0]

STK_FAULT_ERR

Write '1': Reset the fault condition.

Write '0': No effect

Read '1': Stack fault input (FAULTH±) is too noisy or is running at the wrong frequency.

Note: The STK_FAULT_ERR flag may not be clearable under some conditions. If a

STK_FAULT_ERR is detected, and then no more edges appear on the high-side fault pins (as

would be the case if the chip above had a fault condition), it may be impossible to clear the

STK_FAULT_ERR flag. Once proper signaling resumes on the high-side fault pin, it will again be

possible to clear this fault.

Masked STK_FAULT_ERR is not cleared during initialization. As a result, there is a approximately

5-µs window at startup where, if the high-side fault receiver detects more than four falling edges,

the STK_FAULT_ERR will be set even though it is masked.

BQ76PL455APFCT Datasheet(PDF) 83 Page - Texas Instruments

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