BQ76PL455APFCT datasheet(44/125 Pages) TI1

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bq76PL455A

SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

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Device Functional Modes (continued)

•

Internal VP regulator is on and attempting to drive the NPNB signal, but VP remains below the internal VP

POR threshold for longer than VPSD_DLY.

NOTE

Once in the SHUTDOWN state, the part must be re-awakened to continue normal

operations. See Wakeup Behavior from SHUTDOWN.

7.4.2 Wakeup

The bq76PL455A device will wake up and enter the IDLE state when either of the following conditions occurs:

•

WAKEUP pin is high

•

COMML pins receive the WAKE tone

7.4.3 Wakeup Behavior from SHUTDOWN

The WAKEUP pin can bring the part from the SHUTDOWN state to the IDLE state. It can do this in any stack

position. However, typically only the base device uses it when driven from a microcontroller. The pin is level

sensitive and is normally at a low (logic-zero) level. When the part is in SHUTDOWN and the WAKEUP pin

becomes high, the part will transition from SHUTDOWN to IDLE. After applying the high signal, the WAKEUP pin

must de-assert and then return to the low state to allow the part to enter SHUTDOWN again. Upon changing

state, the bq76PL455A will briefly transmit a differential wakeup tone on its COMMH+ and COMMH– pins to the

next higher bq76PL455A, where that device's COMML+ and COMML– pins receives it.

NOTE

The WAKEUP pin is usually kept in the de-asserted (low) state. If the pin is asserted

(high) and then the device is commanded to SHUTDOWN, it will immediately reawaken

and become IDLE. To prevent unexpected state transitions, this pin must not be floating.

Make sure that the pin does not float if the device driving the pin has no power.

The bottom (southernmost) device in the stack sends the wakeup tone out of the COMMH pins in response to

the WAKEUP pin assertion. The next device to the north receives the WAKEUP tone on its COMML pins. It

awakens, which in turn sends the WAKEUP tone to the next device above it. The WAKEUP tone propagates up

the stack in this way to wake all devices in the stack. While the part is in SHUTDOWN, the COMML pins are in

receive mode, and no transmission will occur.

7.4.4 Power-On Reset (POR) or Wakeup

The IC's state machine fully resets at wakeup. Wakeup causes the VP/VDIG output to come up, which in turn

brings up VDD18, providing power to portions of the analog circuits and to all of the core logic, including the

registers and the EEPROM. This is effectively a POR of the part. All registers are loaded with values stored in

EEPROM. Registers that are not loaded from EEPROM reset to their default values indicated in Table 7.

NOTE

Immediately following a reset for any reason, some faults are not valid (=0) until a sample

is taken. All fault bits in registers FAULT_UV, FAULT_OV, and FAULT_AUX are invalid. In

addition, bits FAULT_DEV[HREF_FAULT, HREF_GND_FAULT] are also invalid. Reading

a fault register will not cause the taking of a sample or updating of the bits. A command

must be sent to the device to sample all channels to update the above listed fault bits,

making them valid.

BQ76PL455APFCT Datasheet(PDF) 44 Page - Texas Instruments

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