BQ76PL455APFCT datasheet(24/125 Pages) TI1

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bq76PL455A

SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

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(1)

Oversampling (averaging) is not available for this measurement.

(2)

TSTCONFIG[MODULE_MON_EN] determines whether 2 conversions or 1 conversion takes place.

Table 2. Channel Sample Period Settings

CHANNEL

FIRST SAMPLE

OTHER SAMPLES (AVERAGING)

CMD_OVS_CYCLE=0

CMD_OVS_CYCLE=1

VSENSEn (n=1..16)

ADC_PERIOD_VOL

CMD_OVS_HPER

ADC_PERIOD_VOL

AUXn (n=0..7)

ADC_PERIOD_AUXn

CMD_OVS_GPER

ADC_PERIOD_AUXn

DIGITAL DIE TEMP(1)

Approximately 50 µs

n/a

ANALOG DIE TEMP

ADC_PERIOD_TEMP

CMD_OVS_HPER

VDD18

Approximately 30 µs

CMD_OVS_GPER

ANALOG DIE VREF

ADC_PERIOD_REF

CMD_OVS_HPER

MODULE MONITOR(2)

ADC_PERIOD_MON

CMD_OVS_HPER

ADC_PERIOD_VM

CMD_OVS_HPER

(1)

Sampling periods and averaging mode will affect device accuracy. Device accuracy and register settings (including the sampling period)

used to achieve stated device accuracy are specified under "Electrical Characteristics, ADC" in Analog-to-Digital Converter (ADC):

Analog Front End. Other settings are possible. Device accuracy is not assured at settings other than those specified in the Electrical

Characteristics tables.

(2)

Other register settings used: OVERSMPL = 0x7B; PWRCONFIG = 0x80

(3)

This is not a programmable parameter. No averaging is performed, but there is an inherent delay in the design for the ADC

measurement of the die temperature.

The ADC_PERIOD_VOL bits set the period between ADC samples for the indicated channels whether

oversampling or not. When CMD_OVS_CYCLE = 1, the oversampling period of the Cell and AUX channels

remains

fixed

the

single

sample

period

CELL_SPER[ADC_PERIOD_VOL]

and

AUX_SPER[ADC_PERIOD_AUX], respectively. Otherwise, if CMD_OVS_CYCLE = 0, then the oversample

period for the Cell channels is set by bits CMD_OVS_HPER and for the AUX channels is CMD_OVS_GPER.

CMD_OVS_HPER must be programmed to 12.6 µs and CMD_OVS_GPER can be programmed between 4.13

µs and 12.6 µs in the OVERSMPL register.

After the initial sample period performed per a single sample, oversampling on all other channels are at the

CMD_OVS_GPER and CMD_OVS_HPER period settings as indicated in Table 2.

Writing to the CMD register is used to start the voltage sampling process. This is usually done with a

BROADCAST Write_With_Response_Command sent to the CMD register. Using the BROADCAST version of

the synchronously sample channels command will result in all devices in the stack sampling at the same time.

That is, all devices begin sampling their respective cells, then AUX, and so on, simultaneously.

7.3.3.3 Recommended Sample Periods

Refer to Table 3 for initial recommended settings. Other settings are possible; see the Application and

Implementation section for additional information.

Table 3. ADC Recommended Sample Periods and Setup

MEASURED

PARAMETER

PERIOD (1)

PERIOD REGISTER(2)

1st SAMPLE

SAMPLES 2–8

NAME

AS SHIPPED

VCELL

60 µs

12.6 µs

CELL_SPER

0xBC

VAUX

12.6 µs

AUX_SPER

0x44444444

VMODULE

1000 µs

12.6 µs

TEST_SPER

0xF999

Die Temp (ANL)

100 µs

12.6 µs

CELL_SPER

0xBC

Die Temp (DIG)

50 µs(3)

N/A

30 µs

12.6 µs

TEST_SPER

0xF999

VDD18

30 µs

12.6 µs

N/A

REF2

30 µs

12.6 µs

TEST_SPER

0xF999

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