BQ76PL455APFCT datasheet(74/125 Pages) TI1

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bq76PL455A

SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

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7.6.3.13

CBCONFIG 0x13 (19) Balance Configuration

BIT

NAME

DESCRIPTION

[7:4]

BAL_TIME

This sets the time that balancing will be enabled before it is automatically disabled. This is separate

from the communication timeout counter and is not reset by communication. The counter is reset any

time the BALANCE_EN register is written with a non-zero value.

0 = Until stopped (timer disabled)

1 = 1 second

2 = 1 minute

3 = 2 minutes

4 = 5 minutes

5 = 10 minutes

6 = 15 minutes

7 = 20 minutes

8 = 30 minutes

9 = 60 minutes

10–15 = Reserved

[3]

BAL_CONTINUE

This controls how CBENBL[BALANCE_EN] bits are handled when faults occur.

0 = CBENBL is set to 0 when any fault bit is set, except CUST_CKSUM_ERR, which is ignored.

1 = CBENBL is not changed if a fault occurs.

[2:0]

RSVD

Reserved — always write/read as zero.

7.6.3.14 CBENBL 0x14–15 (20–21) Balancing Enable

BIT

NAME

DESCRIPTION

[15:0]

BALANCE_EN

When EQ_SQUEEZE_EN = 0, these bits control the channels which are balancing. When

EQ_SQUEEZE_EN = 1, these bits control the squeeze resistors used in open-wire-detection (OWD).

BALANCE_EN[0] controls pin EQ1 for balancing cell1, bit1 controls EQ2, and so forth.

For each bit:

0 = Balancing (or squeeze) is disabled on this channel.

1 = Balancing (or squeeze) is enabled on this channel.

If BAL_CONTINUE = 0, all bits in this register will be set to '0' and writes will be ignored if any fault bit

(except CUST_CKSUM_ERR) is set. CUST_CKSUM_ERR is ignored.

If BAL_CONTINUE = 1, fault bits have no effect on this register.

7.6.3.15 TSTCONFIG 0x1E–1F (30–31) Test Configuration

BIT

NAME

DESCRIPTION

[15:12]

RSVD

Reserved — always write/read as zero.

[11:8]

LDO_TEST

These bits directly control the VDD18 LDO test. Set to 0 for normal operation. For additional

information, contact a representative at Texas Instruments.

[7]

CCNT_RST_OFF

When this bit is set, the communication counter does not reset when a valid communications packet is

received, allowing the communications timeout counters to be tested.

Do not change COMM_PD_PER while this bit is set:

•

If COMM_PD_PER is inadvertently set to a value less than COMM_TIM_CNT while this bit is set,

the communications timeout may be missed and not occur for up to 70 min after loss of

communications.

•

If COMM_PD_PER is inadvertently written while this bit is set, writing a new value to

COMM_TIM_CNT (new value before the timeout should occur) will avoid the issue.

[6]

VDIG_TEST

This bit is used to cause the device to enter SHUTDOWN when the VDIGDDIEPOR is tripped as part of a

suite of self-test functions.

Note: Once set, subsequently clearing this bit will not disable this control even though the bit will read 0.

It will not be disabled until the device enters shutdown.

[5]

RSVD

Reserved — always write as zero.

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