BQ76PL455APFCT datasheet(37/125 Pages) TI1

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SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

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7.3.12.3.1

Fault Output Control

FO_CTRL allows groups of enabled faults to drive the pin when the appropriate bit is set. When the register bit is

set, any fault of the indicated type will cause the assertion of the fault outputs (FAULTL, FAULT_N) if they are

enabled—that is, FAULT_N will be driven low and the tone on FAULTL pins will be stopped.

The following groups of faults are enabled in this register (see FO_CTRL 0x6E–6F (110–111) Fault Output

Control for bit position details):

•

Any UV fault (VSENSE inputs)

•

Any OV fault (VSENSE inputs)

•

Any UV fault (AUX inputs)

•

Any OV fault (AUX inputs)

•

Any UV fault (window comparators)

•

Any OV fault (window comparators)

•

Any communications fault (see FAULT_COM)

•

Any system fault (see FAULT_SYS)

•

Any device fault (see FAULT_DEV)

•

Any GPIO fault (see FAULT_GPI)

7.3.12.3.2

Fault Masking

The following registers can enable or mask fault sources individually or in groups. Masking a fault prevents it

from being set, but does not clear an existing fault bit.

•

MASK_COMM—Communications related faults

•

MASK_SYS—System faults in power supplies, over temperature, and so on

•

MASK_DEV—Internal register-checksum faults, and so on

•

GP_FLT_IN—GPIO input level faults

•

NCHAN—Masks faults for unused channels, turns off window comparators for unused channels

7.3.12.4 Fault Latching

When UNLATCHED_FAULT is set, the bits in some of the fault registers (see the following text and Register

Details for included registers) will automatically clear when the fault condition goes away. Continuously set faults

will clear when the condition goes away. Faults set by an event will clear when the event occurs (such as a

sampled channel will clear when that channel is sampled). In this mode, writing to the included fault registers will

have no effect. Unlatched faults, when detected and cleared, can result in creating transient behavior for the

associated flag bits, FAULT_N, and FAULTL.

Changes to the DEVCONFIG[UNLATCHED_FAULT] bit should only occur while no fault bits are set. The

latched/unlatched status of fault bits is undefined when the UNLATCHED_FAULT bit changes while a fault

bit = 1.

Fault bits in the following registers are unaffected by the DEVCONFIG[UNLATCHED_FAULT] bit and are always

latched:

•

FAULT_COM—All bits

•

FAULT_SYS—All bits, except INT_TEMP_FAULT

•

FAULT_DEV—All bits

The DEVCONFIG[UNLATCHED_FAULT] bit, when set, prevents the latching of fault bits in the following

registers:

•

FAULT_UV—Undervoltage VSENSE ADC limit exceeded

•

FAULT_OV—Overvoltage VSENSE ADC limit exceeded

•

FAULT_AUX—Programmable AUX threshold in AUXn_UV or AUXn_OV exceeded

•

FAULT_2UV—Undervoltage VSENSE secondary protection comparator limit exceeded

•

FAULT_2OV—Overvoltage VSENSE secondary protection comparator limit exceeded

•

FAULT_SYS—INT_TEMP_FAULT bit only

•

FAULT_GPI—GPIO (programmable) logic input level triggered a fault

BQ76PL455APFCT Datasheet(PDF) 37 Page - Texas Instruments

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