BQ76PL455APFCT datasheet(92/125 Pages) TI1

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bq76PL455A

SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

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7.6.3.77 AX4OFFSET 0xDC–DD (220–221) AUX4 Offset Correction

BIT

NAME

DESCRIPTION

[15:10]

RSVD

Reserved — always write/read as zero

[9:0]

AUX_COFFSET4

User offset-adjustment register for AUX0 input. This 2's complement value will be added to the AUX

channel. The range is approximately –38.99 mV to 39.06 mV full scale in 1023 steps. The offset is

approximately equal to (5 V × AUXCOFFSET4 / 216). See Section AUX Channel Post-Assembly

Calibration Adjustment for details. It can be used to compensate for offsets induced by the user

design or PCB mounting.

7.6.3.78 AX5OFFSET 0xDE–DF (222–223) AUX5 Offset Correction

BIT

NAME

DESCRIPTION

[15:10]

RSVD

Reserved — always write/read as zero

[9:0]

AUX_COFFSET5

User offset-adjustment register for AUX0 input. This 2's complement value will be added to the AUX

channel. The range is approximately –38.99 mV to 39.06 mV full scale in 1023 steps. The offset is

approximately equal to (5 V × AUXCOFFSET5 / 216). See text for details. It can be used to

compensate for offsets induced by the user design or PCB mounting.

7.6.3.79 AX6OFFSET 0xE0-E1 (224–225) AUX6 Offset Correction

BIT

NAME

DESCRIPTION

[15:10]

RSVD

Reserved — always write/read as zero

[9:0]

AUX_COFFSET6

User offset-adjustment register for AUX0 input. This 2's complement value will be added to the AUX

channel. The range is approximately –38.99 mV to 39.06 mV full scale in 1023 steps. The offset is

approximately equal to (5 V × AUXCOFFSET6 / 216). See text for details. It can be used to

compensate for offsets induced by the user design or PCB mounting.

7.6.3.80 AX7OFFSET 0xE2-E3 (226–227) AUX7 Offset Correction

BIT

NAME

DESCRIPTION

[15:10]

RSVD

Reserved — always write/read as zero

[9:0]

AUX_COFFSET7

User offset-adjustment register for AUX0 input. This 2's complement value will be added to the AUX

channel. The range is approximately –38.99 mV to 39.06 mV full scale in 1023 steps. The offset is

approximately equal to (5 V × AUXCOFFSET7 / 216). See text for details. It can be used to

compensate for offsets induced by the user design or PCB mounting.

7.6.3.81 TSTR_ECC 0xE6-ED (230–237) ECC Test Result[1:0]

BIT

NAME

DESCRIPTION

[31:0]

ECC_TEST_RSLT(x)

These values display the test result from running an ECC test using the TEST_CTRL[ECC_TEST]

bits.

Expected output for Correctable User ECC Test 0x18C3 FF8A 68A9 8069.

Expected output for Correctable Factory ECC Test 0xCC72 D182 80BA 9767.

Expected output for non-correctable User and Factory ECC tests is 0x0000 0000 0000 0000.

7.6.3.82 CSUM 0xF0–F3 (240–243) Checksum

BIT

NAME

DESCRIPTION

[31:0]

USER_CKSUM

This register contains the programmed checksum for the registers. See Table 7, column "CS" for

included registers. The FAULT_DEV[USER_CKSUM_ERR] flag will be set when this value does not

match the internally calculated value shown in CSUM_RSLT 0xF4–F7(244–247) Checksum Readout.

7.6.3.83 CSUM_RSLT 0xF4–F7(244–247) Checksum Readout

BIT

NAME

DESCRIPTION

[31:0]

USER_CKSUM_RD

This register contains the current internally calculated checksum for the registers.

BQ76PL455APFCT Datasheet(PDF) 92 Page - Texas Instruments

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