BQ76PL455APFCT datasheet(31/125 Pages) TI1

31 / 125 page

bq76PL455A

www.ti.com

SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

Product Folder Links: bq76PL455A

Submit Documentation Feedback

7.3.11 Register and EEPROM

7.3.11.1 Error Check and Correct (ECC) EEPROM

storage locations at the same addresses, referred to as shadow registers. The volatile registers are for reading,

writing, and device control. For a list of registers included in the EEPROM, see Table 7.

At wakeup, the bq76PL455A first loads all shadow registers with default values from Register Summary. Then

the bq76PL455A loads the registers conditionally with EEPROM contents from the results of the Error Check and

Correct (ECC) evaluation of the EEPROM.

The EEPROM is loaded to shadow registers in 64-bit blocks; each block has its own Error Check and Correct

(ECC) value stored. The ECC detects a single bit (Single-Error-Correction) or double bit (Double-Error-Detection)

changes in EEPROM stored data.

The ECC is calculated for each block, individually. Single-bit errors are corrected, double-bit errors are only

detected, not corrected. A block with good ECC is loaded. A block with a single-bit error is corrected, and either

FAULT_DEV[USER_ECC_COR] or FAULT_DEV[FACT_ECC_COR] bit is set to flag the corrected error event.

The block is loaded to shadow registers after the single-bit error correction. Since the evaluation is on a block-by-

block basis, it is possible for multiple blocks to have a single-correctable error per block and still be loaded

correctly. Multiple bit errors can exist with full correction, as long as they are limited to a single error per block.

block

with

bad

ECC

comparison

(two

bit

errors

one

block)

not

loaded

and

the

FAULT_DEV[USER_ECC_ERR] or FAULT_DEV[FACT_ECC_ERR] bit is set to flag the failed bit-error event.

The default value remains in the register. This allows some blocks to be loaded correctly (no fail or single bit

corrected value) and some blocks not to load. Any time either of the FAULT_DEV[*_ECC_ERR] is set, and the

condition is not cleared by a soft reset, the device has failed and should not be used.

7.3.12 FAULT Sensing and Signaling

A dedicated differential FAULT link allows each bq76PL455A in a stack of devices to signal the presence of any

monitored and active/latched fault condition to the main microcontroller separately from the UART link. The

FAULTH+/– and

FAULTL+/– pins

implement

AC-coupled

differential-signaling

scheme

similar

communication pins COMML+/– and COMMH+/–, but using only a simple heartbeat signal to indicate normal or

fault conditions by the presence or absence of a repetitive pulse, respectively. The low duty-cycle heartbeat

stops anytime it senses a fault and the fault condition sets a bit in one of the FAULT_* registers. Masked faults

have no effect on the heartbeat generation.

BQ76PL455APFCT Datasheet(PDF) 31 Page - Texas Instruments

BQ76PL455APFCT Datasheet(HTML) 31 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL