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BQ76PL455APFCT Datasheet(PDF) 43 Page - Texas Instruments

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Part # BQ76PL455APFCT
Description  16-Cell Industrial Integrated Battery Monitor
PDF  125 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

BQ76PL455APFCT Datasheet(HTML) 43 Page - Texas Instruments

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bq76PL455A
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SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016
Product Folder Links: bq76PL455A
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Copyright © 2016, Texas Instruments Incorporated
7.3.12.10 Communications Timeout Counters
Check the communication timeout counters by setting and reading the 24 most-significant bits of the timeout
counter using COMM_TIM_CNT. A 4-kHz clock source drives the timeout counter. To aid this testing,
CCNT_RST_OFF may be set so the communication sent to either set or monitor the counter does not reset the
counter. The counter value may be set using COMM_TIM_CNT to enable faster testing of long periods. The bits
that are not accessible are set to '1' by writing to this register, to test the counter rollovers quickly.
7.3.13 Built-in-Test Functions
To access the built-in-test functions, set bits in the various registers. The identification of these bits are in the
descriptions of the appropriate registers and their bits in Register Details.
7.3.13.1 Safety Manual and FMEDA
The Safety Manual for bq76PL455A-Q1 (SLUUB67) is available on ti.com. Please contact your TI Sales
Associate or Applications Engineer for the bq76PL455A-Q1 FMEDA (SLUUB93).
7.4 Device Functional Modes
The bq76PL455A device has three power states (modes):
•
SHUTDOWN (sleep)—The lowest power state used for long periods of inactivity to extend battery life.
•
IDLE—The default condition when awake and ready to receive and execute commands.
•
ACTIVE—The highest power state while communicating; that is, IDLE + communications activity.
7.4.1 SHUTDOWN
SHUTDOWN is the lowest power state available in the part. In this state, power is off and monitoring disabled for
most internal blocks. Typically, SHUTDOWN is for long periods of inactivity when the battery is not being
charged or discharged. The part must receive a high signal on the WAKEUP pin or a WAKEUP tone through the
vertical communications bus to transition to the IDLE state.
To enter SHUTDOWN, remove external voltage sources of VP, VDIG, and all input voltage sources to AUX pins
and other I/O pins. VIO can remain while in SHUTDOWN mode and GPIO can remain if based on VIO. While in
SHUTDOWN mode, VP and VDIG must remain off or be disabled to avoid back powering the bq76PL455A
through internal ESD structures. When VIO is lowered, the bq76PL455A will immediately go into reset. Holding
VIO for longer than VIOSD_DLY MAX will cause the device to enter SHUTDOWN mode.
The WAKEUP pin must be held in the low state to allow the device to enter and remain in the SHUTDOWN state
(setting the pin low does not place the device in SHUTDOWN). If the WAKEUP pin remains in the high state, the
device will cycle off and immediately back on. Operation is unpredictable if the WAKEUP pin floats, so take care
to keep this pin in a defined state. This is not harmful to the device, but may not provide the expected behavior in
the system.
If the NPN circuit is not used (external supply), VP and VDIG should turn off immediately after entering shutdown
mode. Lowering VP and VDIG will also put the device in SHUTDOWN mode.
The part will enter SHUTDOWN when any of the following conditions occur:
•
The user requested SHUTDOWN through a command by asserting DEV_CTRL[PWRDN], usually with a
broadcast form of the command. The WAKEUP pin on the base bq76PL455A must remain in the low state.
•
There was a communications timeout caused by the timer set in register CTO[COMM_PD_PER] due to:
–
No valid frames (packets) received in the set period, <OR>
–
TSTCONFIG[CCNT_RST_OFF] is set and the timer expired whether valid frames were received or not,
usually as a part of BIST.
•
TSTCONFIG[VDIG_TEST] was set at some time since the last SHUTDOWN <AND> VDIG dropped below its
SHUTDOWN threshold (DDIEPOR). Once set, subsequently clearing TSTCONFIG[VDIG_TEST] will not
disable this control even though the bit will read 0. It will not disable until the device enters shutdown.
•
One of the two thermal shutdown (TSD) circuits sensed an overtemperature condition (there is one sensor on
each die that operates separately, with separate register flag indicators).
•
VIO was below its VIOPOR threshold for longer than VIOSD_DLY.
•
V5VAO was below the V5VAOSD POR threshold.



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