BQ76PL455APFCT datasheet(36/125 Pages) TI1

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bq76PL455A

SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016

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The differential signal lines are isolated between ICs by a DC blocking capacitor similar to the differential

communications VBUS daisy chain. The capacitor typical rating is at a minimum of two times the stack voltage to

provide plenty of standoff margins to handle system faults that expose the device to local hazardous voltages.

One capacitor is sufficient for the normal operation of the device. The system designer may elect to use two

capacitors, one at each end of the cable or PCB wiring, for an additional safety factor. In this case, use double

the capacitor value from the normal requirement, so that the two capacitors in series result in the same value in

the signal path.

The heartbeat derivation comes from the device main oscillator and is generated separately out of each device in

the

stack.

The

device

does

not

copy

re-transmit

the

value

from

the

device

above

it.

The

FAULT_COM[STK_FAULT_ERR] that indicates a problem with the fault heartbeat is sensed individually by each

device in the stack and may be tripped in some devices and not in others under some fault conditions.

The FAULT_N pin signals faults from both internal sources and from ICs above in the stack, if enabled. Internal

faults are on FAULT_N depending on the enabled sources in the FO_CTRL register. Faults from stacked devices

above it are signaled on the FAULT_N pin when enabled by COMCONFIG[FAULT_HIGH_EN]. The FAULT_N

pin always outputs a low signal in reset or shutdown.

7.3.12.3 Fault Sensing

Masking of fault sources may be in registers MASK_COMM, MASK_SYS, and MASK_DEV. Masking a fault will

prevent the flag from being set at a future time, but it will not clear an already set fault flag.

Any time an unmasked fault condition is triggered, the device sets a bit in the appropriate FAULT_* register at

addresses 0x52–63.

When a device senses an unmasked fault or, with enabled fault communications, when the heartbeat from the

device above stops, the FAULT_N pin asserts low to signal the fault to a user circuit or microcontroller. Each

device in the stack that sees one of these conditions asserts the FAULT_N pin if the UART_EN bit in

COMCONFIG is set. The heartbeat stop and FAULT_N pin assertions occur simultaneously.

Normally, after RESET, POR, or normal wakeup, user firmware must clear FAULT_SYS[SYS_RESET] to start

the heartbeat. If there is an enabled stack communications interface, the heartbeat will start after clearing

SYS_RESET and receiving four cycles of the heartbeat on the north-interface FAULTH pins. This typically

requires a little more than approximately 400 µs and results in clearing the STATUS[STACK_FAULT] flag.

Faults propagate down the stack through the FAULTL pins. The lower of two adjacent bq76PL455A devices

monitors its FAULTH pins for the propagated faults from the device above it in the stack.

When COMCONFIG[FAULT_HIGH_EN] = 1, the logic will monitor the receiver for falling edges. Under-frequency

conditions will set the STATUS[STACK_FAULT_DET] and STATUS[STACK_FAULT] flags. Note that this allows

every other pulse to be lost without reporting an error.

Over-frequency conditions will set the FAULT_COM[STK_FAULT_ERR] flag. Once proper signaling resumes on

the high-side fault pin, it will again be possible to clear this fault.

The fault heartbeat stops and FAULT_N asserts during any of the following conditions:

•

The fault heartbeat stops on the high-side fault interface FAULTH pins (if not configured to ignore it)

•

Some automatic feature in the device detects a fault; that is, the secondary protector VSENSE comparators,

checksum failure, automatic internal temperature sampling, and so forth

•

A command to sample returned a value that was out of range and caused a fault

•

An internal self-test fails

NOTE

The STK_FAULT_ERR may not be clearable under some conditions.

1. If a STK_FAULT_ERR is detected and then no more edges appear on the high-side fault pins

(as would be the case if the chip above had a fault condition), it may be impossible to clear the

STK_FAULT_ERR flag.

2. A masked STK_FAULT_ERR does not clear during initialization. As a result, there is an

approximately 4.5-µs window at startup during which, if the high-side fault receiver detects more

than four falling edges, STK_FAULT_ERR will be set even though it is masked.

BQ76PL455APFCT Datasheet(PDF) 36 Page - Texas Instruments

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