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BQ76PL455APFCT Datasheet(PDF) 81 Page - Texas Instruments |
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BQ76PL455APFCT Datasheet(HTML) 81 Page - Texas Instruments |
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81 / 125 page  81 bq76PL455A www.ti.com SLUSCL0A – SEPTEMBER 2016 – REVISED OCTOBER 2016 Product Folder Links: bq76PL455A Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated BIT NAME DESCRIPTION [1] NEW_DATA This read-only bit indicates ADC conversion data are available when set. Writing to the bit has no effect. The bit is reset by reading any conversion result (sample) data. This can be used to tell if some new data have been collected since the last COMMAND to report sample data. This only indicates if some sample has been collected since the last report. It does not track what channel was reported or collected. This bit will not be set by the automatic internal temperature sampling or initialization sampling. [0] SYS_INIT Write '1': Stop waiting for VM and continue with initialization. Write '0': No effect Read '0': System initialization is complete. Read '1': System initialization is in progress. This can be useful to speed up the wakeup sequence. Device accuracy may be impaired and is not specified until VM is in the correct range. This is useful when waking the device quickly for self-testing purposes or performing tests that will cause shutdown or reset. Setting this bit allows code to perform other functions while waiting for VM to ramp up. 7.6.3.27 FAULT_SUM 0x52–53 (82–83) Fault Summary BIT NAME DESCRIPTION [15] UV_FAULT_SUM For each of these bits: Write '1': Reset all fault conditions of this type. Write '0': No effect Read '1': One or more of the individual fault bits of this type are currently set. These bits always reflect the state of the underlying bits in the other fault registers, which may be latched or not, depending on the setting of the DEVCONFIG[UNLATCHED_FAULT] bit. [14] OV_FAULT_SUM [13] AUXUV_FAULT_SUM [12] AUXOV_FAULT_SUM [11] CMPUV_FAULT_SUM [10] CMPOV_FAULT_SUM [9] COMM_FAULT_SUM [8] SYS_FAULT_SUM [7] CHIP_FAULT_SUM [6] GPI_FAULT_SUM [5:0] RSVD Reserved — always read as zero. 7.6.3.28 FAULT_UV 0x54–55 (84–85) Cell Undervoltage Fault BIT NAME DESCRIPTION [15:0] UV_FAULT For each bit in this bitmask: Write '1': Reset the fault condition. Write '0': No effect Read '1': The stored result for the corresponding battery channel is less than UV_THRES_CELL. UV_FAULT[0] corresponds to cell 1. If UNLATCHED_FAULT is set, this register is self-clearing. 7.6.3.29 FAULT_OV 0x56–57 (86–87) Cell Overvoltage Fault BIT NAME DESCRIPTION [15:0] OV_FAULT For each bit in this bitmask: Write '1': Reset the fault condition. Write '0': No effect Read '1': The stored result for the corresponding battery channel is greater than OV_THRES_CELL. OV_FAULT[0] corresponds to cell 1. If UNLATCHED_FAULT is set, this register is self-clearing. |
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