MM912F634CV2AP datasheet(110/335 Pages) FREESCALE

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Functional Description and Application Information

Serial Communication Interface (S08SCIV4)

MM912F634

Freescale Semiconductor

110

4.15.2.2

SCI Control Register 1 (SCIC1)

This read/write register is used to control various optional features of the SCI system.

Table 128. SCI Control Register 1 (SCIC1)

Offset(91) 0x42

Access: User read/write

543

210

LOOPS

RSRC

ILT

Reset

000

Note:

91. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 129. SCIC1 Field Descriptions

Field

Description

LOOPS

Loop Mode Select

— Selects between loop back modes and normal 2-pin full-duplex modes. When LOOPS = 1, the

transmitter output is internally connected to the receiver input.

0 Normal operation — RxD and TxD use separate pins.

1 Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD

pin is not used by SCI.

RSRC

Receiver Source Select

— This bit has no meaning or effect unless the LOOPS bit is set to 1. When LOOPS = 1, the receiver

input is internally connected to the TxD pin and RSRC determines whether this connection is also connected to the transmitter

output.

0 Provided LOOPS = 1, RSRC = 0 selects internal loop back mode and the SCI does not use the RxD pins.

1 Single-wire SCI mode where the TxD pin is connected to the transmitter output and receiver input.

9-Bit or 8-Bit Mode Select

0 Normal — start + 8 data bits (LSB first) + stop.

1 Receiver and transmitter use 9-bit data characters

start + 8 data bits (LSB first) + 9th data bit + stop.

ILT

Idle Line Type Select

— Setting this bit to 1 ensures that the stop bit and logic 1 bits at the end of a character do not count

toward the 10 or 11 bit times of logic high level needed by the idle line detection logic. Refer to Section 4.15.3.3.2.1, “Idle-line

Wake-up"” for more information.

0 Idle character bit count starts after start bit.

1 Idle character bit count starts after stop bit.

Parity Enable

— Enables hardware parity generation and checking. When parity is enabled, the most significant bit (MSB) of

the data character (eighth or ninth data bit) is treated as the parity bit.

0 No hardware parity generation or checking.

1 Parity enabled.

Parity Type

— Provided parity is enabled (PE = 1), this bit selects even or odd parity. Odd parity means the total number of 1s

in the data character, including the parity bit, is odd. Even parity means the total number of 1s in the data character, including

the parity bit, is even.

0 Even parity.

1 Odd parity.

MM912F634CV2AP Datasheet(PDF) 110 Page - Freescale Semiconductor, Inc

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