MM912F634CV2AP datasheet(113/335 Pages) FREESCALE

113 / 335 page

Functional Description and Application Information

Serial Communication Interface (S08SCIV4)

MM912F634

Freescale Semiconductor

113

4.15.2.5

SCI Status Register 2 (SCIS2)

This register has one read-only status flag.

Framing Error Flag

— FE is set at the same time as RDRF when the receiver detects a logic 0 where the stop bit was

expected. This suggests the receiver was not properly aligned to a character frame. To clear FE, read SCIS1 with FE = 1 and

then read the SCI data register (SCID).

0 No framing error detected. This does not guarantee the framing is correct.

1 Framing error.

Parity Error Flag

— PF is set at the same time as RDRF when parity is enabled (PE = 1) and the parity bit in the received

character does not agree with the expected parity value. To clear PF, read SCIS1 and then read the SCI data register (SCID).

0 No parity error.

1 Parity error.

Table 134. SCI Status Register 2 (SCIS2)

Offset(94) 0x45

Access: User read/write

543

210

LBKDIF

RXEDGIF

RXINV(92)

RWUID

BRK13

LBKDE

RAF

Reset

000

Note:

94. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 135. SCIS2 Field Descriptions

Field

Description

LBKDIF

LIN Break Detect Interrupt Flag

— LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break character is

detected. LBKDIF is cleared by writing a “1” to it.

0 No LIN break character has been detected.

1 LIN break character has been detected.

RXEDGIF

RxD Pin Active Edge Interrupt Flag

— RXEDGIF is set when an active edge (falling if RXINV = 0, rising if RXINV=1) on the

RxD pin occurs. RXEDGIF is cleared by writing a “1” to it.

0 No active edge on the receive pin has occurred.

1 An active edge on the receive pin has occurred.

RXINV(95)

Receive Data Inversion

— Setting this bit reverses the polarity of the received data input.

0 Receive data not inverted

1 Receive data inverted

RWUID

Receive Wake Up Idle Detect

— RWUID controls whether the idle character that wakes up the receiver sets the IDLE bit.

0 During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character.

1 During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character.

BRK13

Break Character Generation Length

— BRK13 is used to select a longer transmitted break character length. Detection of a

framing error is not affected by the state of this bit.

0 Break character is transmitted with length of 10 bit times (11 if M = 1)

1 Break character is transmitted with length of 13 bit times (14 if M = 1)

LBKDE

LIN Break Detection Enable

— LBKDE is used to select a longer break character detection length. While LBKDE is set, framing

error (FE) and receive data register full (RDRF) flags are prevented from setting.

0 Break character detection enabled.

1 Break character detection disabled.

Note:

95. Setting RXINV inverts the RxD input for all cases: data bits, start and stop bits, break, and idle.

Table 133. SCIS1 Field Descriptions (continued)

Field

Description

MM912F634CV2AP Datasheet(PDF) 113 Page - Freescale Semiconductor, Inc

MM912F634CV2AP Datasheet(HTML) 113 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL