MM912F634CV2AP datasheet(112/335 Pages) FREESCALE

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Functional Description and Application Information

Serial Communication Interface (S08SCIV4)

MM912F634

Freescale Semiconductor

112

4.15.2.4

SCI Status Register 1 (SCIS1)

This register has eight read-only status flags. Writes have no effect. Special software sequences (which do not involve writing to

this register) are used to clear these status flags.

Table 132. SCI Status Register 1 (SCIS1)

Offset(93) 0x44

Access: User read/write

543

210

TDRE

RDRF

IDLE

Reset

100

Note:

93. Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.

Table 133. SCIS1 Field Descriptions

Field

Description

TDRE

Transmit Data Register Empty Flag

— TDRE is set out of reset and when a transmit data value transfers from the transmit

data buffer to the transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read SCIS1 with TDRE = 1

and then write to the SCI data register (SCID).

0 Transmit data register (buffer) full.

1 Transmit data register (buffer) empty.

Transmission Complete Flag

— TC is set out of reset and when TDRE = 1 and no data, preamble, or break character is being

transmitted.

0 Transmitter active (sending data, a preamble, or a break).

1 Transmitter idle (transmission activity complete).

TC is cleared automatically by reading SCIS1 with TC = 1 and then doing one of the following three things:

•

Write to the SCI data register (SCID) to transmit new data

• Queue a preamble by changing TE from 0 to 1

•

Queue a break character by writing 1 to SBK in SCIC2

RDRF

Receive Data Register Full Flag

— RDRF becomes set when a character transfers from the receive shifter into the receive

data register (SCID). To clear RDRF, read SCIS1 with RDRF = 1 and then read the SCI data register (SCID).

0 Receive data register empty.

1 Receive data register full.

IDLE

Idle Line Flag

— IDLE is set when the SCI receive line becomes idle for a full character time after a period of activity. When

ILT = 0, the receiver starts counting idle bit times after the start bit. So if the receive character is all 1s, these bit times and the

stop bit time count toward the full character time of logic high (10 or 11 bit times depending on the M control bit) needed for the

receiver to detect an idle line. When ILT = 1, the receiver doesn’t start counting idle bit times until after the stop bit. So the stop

bit and any logic high bit times at the end of the previous character do not count toward the full character time of logic high

needed for the receiver to detect an idle line.

To clear IDLE, read SCIS1 with IDLE = 1 and then read the SCI data register (SCID). After IDLE has been cleared, it cannot

become set again until after a new character has been received and RDRF has been set. IDLE will get set only once even if

the receive line remains idle for an extended period.

0 No idle line detected.

1 Idle line was detected.

Receiver Overrun Flag

— OR is set when a new serial character is ready to be transferred to the receive data register (buffer),

but the previously received character has not been read from SCID yet. In this case, the new character (and all associated error

information) is lost because there is no room to move it into SCID. To clear OR, read SCIS1 with OR = 1 and then read the SCI

data register (SCID).

0 No overrun.

1 Receive overrun (new SCI data lost).

Noise Flag

— The advanced sampling technique used in the receiver takes seven samples during the start bit and three

samples in each data bit and the stop bit. If any of these samples disagrees with the rest of the samples within any bit time in

the frame, the flag NF will be set at the same time as the flag RDRF gets set for the character. To clear NF, read SCIS1 and

then read the SCI data register (SCID).

0 No noise detected.

1 Noise detected in the received character in SCID.

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