MM912F634CV2AP datasheet(119/335 Pages) FREESCALE

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Functional Description and Application Information

Serial Communication Interface (S08SCIV4)

MM912F634

Freescale Semiconductor

119

At any time, an active edge on the RxD serial data input pin causes the RXEDGIF flag to set. The RXEDGIF flag is cleared by

writing a “1” to it. This function does depend on the receiver being enabled (RE = 1).

4.15.3.5

Additional SCI Functions

The following sections describe additional SCI functions.

4.15.3.5.1

8- and 9-Bit Data Modes

The SCI system (transmitter and receiver) can be configured to operate in 9-bit data mode by setting the M control bit in SCIC1.

In 9-bit mode, there is a ninth data bit to the left of the MSB of the SCI data register. For the transmit data buffer, this bit is stored

in T8 in SCIC3. For the receiver, the ninth bit is held in R8 in SCIC3.

For coherent writes to the transmit data buffer, write to the T8 bit before writing to SCID.

If the bit value to be transmitted as the ninth bit of a new character is the same as for the previous character, it is not necessary

to write to T8 again. When data is transferred from the transmit data buffer to the transmit shifter, the value in T8 is copied at the

same time data is transferred from SCID to the shifter.

9-bit data mode typically is used in conjunction with parity to allow eight bits of data plus the parity in the ninth bit. Or it is used

with address-mark wake-up so the ninth data bit can serve as the wake-up bit. In custom protocols, the ninth bit can also serve

as a software-controlled marker.

4.15.3.5.2

Stop Mode Operation

During all stop modes, clocks to the SCI module are halted.

In stop1 and stop2 modes, all SCI register data is lost and must be re-initialized upon recovery from these two stop modes. No

SCI module registers are affected in stop3 mode.

The receive input active edge detect circuit is still active in stop3 mode, but not in stop2. An active edge on the receive input

brings the CPU out of stop3 mode if the interrupt is not masked (RXEDGIE = 1).

Note that because the clocks are halted, the SCI module will resume operation upon exit from stop (only in stop3 mode). Software

should ensure stop mode is not entered while there is a character being transmitted out of or received into the SCI module.

4.15.3.5.3

Loop Mode

When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or single-wire mode (RSRC = 1).

Loop mode is sometimes used to check software, independent of connections in the external system, to help isolate system

problems. In this mode, the transmitter output is internally connected to the receiver input and the RxD pin is not used by the SCI,

so it reverts to a general purpose port I/O pin.

4.15.3.5.4

Single-wire Operation

When LOOPS = 1, the RSRC bit in the same register chooses between loop mode (RSRC = 0) or single-wire mode (RSRC = 1).

Single-wire mode is used to implement a half-duplex serial connection. The receiver is internally connected to the transmitter

output and to the TxD pin. The RxD pin is not used and reverts to a general purpose port I/O pin.

In single-wire mode, the TXDIR bit in SCIC3 controls the direction of serial data on the TxD pin. When TXDIR = 0, the TxD pin

is an input to the SCI receiver and the transmitter is temporarily disconnected from the TxD pin so an external device can send

serial data to the receiver. When TXDIR = 1, the TxD pin is an output driven by the transmitter. In single-wire mode, the internal

loop back connection from the transmitter to the receiver causes the receiver to receive characters that are sent out by the

transmitter.

MM912F634CV2AP Datasheet(PDF) 119 Page - Freescale Semiconductor, Inc

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