MM912F634CV2AP datasheet(160/335 Pages) FREESCALE

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Functional Description and Application Information

MM912F634 - MCU Die Overview

MM912F634

Freescale Semiconductor

160

The system clock can be supplied in several ways enabling a range of system operating frequencies to be supported:

•

The on-chip frequency locked loop (FLL).

•

The oscillator.

The clock generated by the FLL or oscillator provides the main system clock frequencies core clock and bus clock. As shown in

Figure 45, these system clocks are used throughout the MCU to drive the core, the memories, and the peripherals.

The Flash memory is supplied by the bus clock which is also being used as a time base to derive the program and erase times

for the NVM.

In order to ensure the presence of the clock the MCU includes an on-chip clock monitor connected to the output of the oscillator.

The clock monitor can be configured to generate a system reset if it is allowed to time out as a result of no oscillator clock being

present.

4.26.6

Modes of Operation

The MCU can operate in different chip modes. These are described in 4.26.6.1 Chip Configuration Summary.

The MCU can operate in different power modes to facilitate power saving when full system performance is not required. These

are described in 4.26.6.2 Power Modes.

Some modules feature a software programmable option to freeze the module status whilst the background debug module is

active to facilitate debugging. This is described in 4.26.6.2.4 Freeze Mode.

4.26.6.1

Chip Configuration Summary

The different modes and the security state of the MCU affect the debug features (enabled or disabled).

The operating mode out of reset is determined by the state of the MODC signal during reset (see Table 214). The MODC bit in

the MODE register shows the current operating mode and provides limited mode switching during operation. The state of the

MODC signal is registered into this bit on the rising edge of RESET.

4.26.6.1.1

Normal Single-chip Mode

This mode is intended for normal device operation. The opcode from the on-chip memory is being executed after reset (requires

the reset vector to be programmed correctly).The processor program is executed from internal memory.

4.26.6.1.2

Special Single-chip Mode

This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The background debug

module BDM is active in this mode. The CPU executes a monitor program located in an on-chip ROM. BDM firmware waits for

additional serial commands through the BKGD pin.

4.26.6.2

Power Modes

The MCU features two main low-power modes. Consult the respective module description for module specific behavior in system

stop and system wait mode. An important source of information about the clock system is the Clock and Reset Generator

description (CRG).

Table 214. Chip Modes

Chip Modes

MODC

Normal single chip

Special single chip

MM912F634CV2AP Datasheet(PDF) 160 Page - Freescale Semiconductor, Inc

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