MM912F634CV2AP datasheet(161/335 Pages) FREESCALE

161 / 335 page

Functional Description and Application Information

MM912F634 - MCU Die Overview

MM912F634

Freescale Semiconductor

161

4.26.6.2.1

System Stop Mode

The system stop mode is entered if the CPU executes the STOP instruction. Asserting RESET, D2DINT, or any other interrupt

that is not masked exits system stop mode. System stop mode can be exited by CPU activity - depending on the configuration

of the interrupt request.

4.26.6.2.2

Wait Mode

This mode is entered when the CPU executes the WAI instruction. In this mode the CPU will not execute instructions. The internal

CPU clock is switched off. All peripherals can be active in system wait mode. For further power reduction the peripherals can

individually turn off their local clocks. Asserting RESET, D2DINT, or any other interrupt that is not masked ends system wait mode.

4.26.6.2.3

Run Mode

Although this is not a low-power mode, unused peripheral modules should be disabled in order to save power.

4.26.6.2.4

Freeze Mode

The COP and RTI module provide a software programmable option to freeze the module status when the background debug

module is active. This is useful when debugging application software. For detailed description of the behavior of the COP and

RTI when the background debug module is active consult the corresponding module descriptions.

4.26.7

Security

4.26.7.1

MC9S12I32

The MCU security feature allows the protection of the on chip Flash. For a detailed description of the security features refer to

the 4.36.6, “Flash Module Security“ description.

4.26.8

Resets and Interrupts

Consult the S12SCPU manual and the 4.27, “Port Integration Module (9S12I32PIMV1)“ description for information on exception

processing.

4.26.8.1

Resets

Resets are explained in detail in the 4.27, “Port Integration Module (9S12I32PIMV1)“ description.

4.26.8.2

Vectors

Table 215 lists all interrupt sources and vectors in the order of priority. The interrupt module (4.27, “Port Integration Module

(9S12I32PIMV1)“) provides an interrupt vector base register (IVBR) to relocate the vectors.

Table 215. Interrupt Vector Locations

Vector Address(146)

Interrupt Source

CCR

Mask

Local Enable

$FFFE

System reset or illegal access reset

None

$FFFC

Oscillator monitor reset

None

CRGCTL0 (CME)

$FFFA

COP watchdog reset

None

COP rate select

Vector base + $F8

Unimplemented instruction trap

None

Vector base+ $F6

SWI

None

Vector base+ $F4

D2DI Error Interrupt

X Bit

None

Vector base+ $F2

D2DI External Error Interrupt

I bit

D2DIE (D2DCTL1)

MM912F634CV2AP Datasheet(PDF) 161 Page - Freescale Semiconductor, Inc

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